[Altera][Q2HB] HandBook
[Altera][Q2HB] HandBook
コレを全部読めれば,設計フローからソフトの使い方から,おおよそ把握できるはず..(総ページ2496)
QuartusIIからヘルプを押下すると,このHandbook内の章や節が分冊されたものを開こうとするでしょう.vざっと何をすべきか,何ができるかを把握するには,こちらを見て脳内indexを生成しておくと効率が良いでしょう*1.
QuartusII Handbook全貌
ファイル:"quartusii_handbook.pdf"
Quartus II Handbook Version 8.1 Volume 1: Design and Synthesis Section I. Design Flows Chapter 1, Design Planning with the Quartus II Software 重要なFPGAデザインの計画について記されます. - device selection - early power estimation - I/O pin planning - design planning 要求事項とALTERAの各種ツールの紹介もあります. Chapter 2, Quartus II Incremental Compilation for Hierarchical and Team-Based Design 無料ツールでサポートしてなさげなので省略. グループ開発をサポートするQuartusの使い方と思想について記述あり. Chapter 3, Quartus II Design Flow for MAX+PLUS II Users MAX+PLUS IIユーザ向けの乗り換え案内? Chapter 4, Quartus II Support for HardCopy Series Devices FPGAで試作,ASICで量産を行う際のフローについて解説? Section II. Design Guidelines Chapter 5, Design Recommendations for Altera Devices and the Quartus II Design Assistant 同期設計の演習と組み合わせ回路の構造とクロックスキームのガイドラインを記す. Design Assistantを使ってデザインルールチェックをする方法を含みます. デバイスアーキテクチャのデザイン指標について考えるときに読むべき...? Chapter 6, Recommended HDL Coding Styles 推奨HDL コーディングスタイルと例示(VHDL/VerilogHDL). ALTERAデバイスアーキ依存のオプション記述についても触れる模様.. Chapter 7, Best Practices for Incremental Compilation Partitions and Floorplan Assignments インクリメンタルコンパイルとフロアプラン設計演習. グループデザインを行う場合に参照すればよい?.無償版では使えないだろう. Section III. Synthesis 論理合成全般. Chapter 8, Quartus II Integrated Synthesis Chapter 9, Synopsys Synplify Support Chapter 10, Mentor Graphics Precision Synthesis Support Chapter 11, Mentor Graphics LeonardoSpectrum Support Chapter 12, Analyzing Designs with Quartus II Netlist Viewers Volume 2: Design Implementation and Optimization Section I. Scripting and Constraint Entry Chapter 1, Assignment Editor Chapter 2, Command-Line Scripting Chapter 3, Tcl Scripting Chapter 4, Managing Quartus II Projects Section II. I/O and PCB Tools Chapter 5, I/O Management Chapter 6, Mentor Graphics PCB Design Tools Support Chapter 7, Cadence PCB Design Tools Support Section III. Area, Timing and Power Optimization Chapter 8, Area and Timing Optimization Chapter 9, Power Optimization Chapter 10, Analyzing and Optimizing the Design Floorplan Chapter 11, Netlist Optimizations and Physical Synthesis Chapter 12, Design Space Explorer Section IV. Engineering Change Management Chapter 13, Engineering Change Management with the Chip Planner Volume 3: Verification Volume 4: SOPC Builder Section I. Simulation Chapter 1, Quartus II Simulator Chapter 2, Mentor Graphics ModelSimSupport Chapter 3, Synopsys VCS Support Chapter 4, Cadence NC-Sim Support Chapter 5, Aldec Active-HDL Support Chapter 6, Simulating Altera IP in Third-Party Simulation Tools Section II. Building Systems with SOPC Builder Chapter 9, SOPC Builder Memory Subsystem Development Walkthrough Chapter 10, SOPC Builder Component Development Walkthrough Section III. Interconnect Components Chapter 11, Avalon Memory-Mapped Bridges Chapter 12, Avalon Streaming Interconnect Components Volume 5: Embedded Peripherals Section I. Off-Chip Interface Peripherals Chapter 1, SDRAM Controller Core Chapter 2, CompactFlash Core Chapter 3, Common Flash Interface Controller Core Chapter 4, EPCS Device Controller Core Chapter 5, JTAG UART Core Chapter 6, UART Core Chapter 7, SPI Core Chapter 8, Optrex 16207 LCD Controller Core Chapter 9, PIO Core Chapter 10, Avalon-ST JTAG Interface Core Chapter 11, Avalon-ST Serial Peripheral Interface Core Chapter 12, SPI Slave/JTAG to Avalon Master Bridge Cores Chapter 13, PCI Lite Core Section II. On-Chip Storage Peripherals Chapter 14, Avalon-ST Single Clock and Dual Clock FIFO Cores Chapter 15, On-Chip FIFO Memory Core Chapter 16, Avalon-ST Multi-Channel Shared Memory FIFO Core Section III. Transport and Communication Chapter 17, Avalon Streaming Channel Multiplexer and Demultiplexer Cores Chapter 18, Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores Chapter 19, Avalon Packets to Transactions Converter Core Chapter 20, Avalon-ST Round Robin Scheduler Core Section IV. Peripherals Chapter 21, Scatter-Gather DMA Controller Core Chapter 22, DMA Controller Core Chapter 23, Video Sync Generator and Pixel Converter Cores Chapter 24, Interval Timer Core Chapter 25, System ID Core Chapter 26, Mutex Core Chapter 27, Mailbox Core Section V. Test and Debug Peripherals Chapter 28, Cyclone III Remote Update Controller Core Chapter 29, Performance Counter Core Chapter 30, Avalon Streaming Test Pattern Generator and Checker Cores
後半抜けてますが,まぁわかるでしょう.
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