Linuxメモ（跡地）

device.tree.org

devicetreeの実装サイドからの仕様を公開していると思われます。

そもそもdevicetreeとはコンピュータシステムの構成要素を記述するために用いられています。

冒頭で 関連している仕様として、以下が挙げられています：

• IEEE 1275 Open Firmware standard―IEEE Standard for Boot (Initialization Configuration) Firmware: Core Requirements and Practices [IEEE1275].
• EPAPR

この仕様書は、2016年からlinaro社, ARM社によって生成されている模様です。

コンピュータシステムの初期化を行う際に、OS起動前に初期化処理の必要なハードウェア類があります。ブートローダ、ハイパーバイザ等が初期化等を行って、最終的にOSへと処理を移します。このプログラム間で情報のやりとりを行うための規定にも使えるもの、とあります。

仕様の詳細は、Devicetree Specificationを参照しましょう。

なぜ必要か

PCでは ACPIがハードウェア情報を提供してくれるため、必要な設定・ドライバのロードが可能でした。

そこで Open Firmwareの頃から powerpcアーキテクチャで devicetreeの利用が始まっていました。その後 Linux kernelソースコードの汚い肥大化をLinusに指摘されたことにより、ARMアーキテクチャにも適用することとなったものです。したがって、poewrpcやARMアーキテクチャのカーネルドライバ・u-bootに関わる方には必須の事項となります。

ブートプログラムがシステム内のハードウェアの初期化処理を行うために必要な情報を得るために必要です。これがなければ、ブートプログラムはシステム内のハードウェア構成にあわせて個々に用意する必要があります。これではブートプログラムの実装効率も悪く、同じようなコードが散乱することになりかねません。そこで、ドライバソフトウェアを個々のハードウェアに対応したものとし、そのリソースを含めて定義できるようにすることでソフトウェアを共通化することができます。

その昔、PC/AT互換機が出てから `Plug and Play` が登場するまでは、ボードのリソース設定等をディップスイッチで行って、インストール作業者がリソース競合を回避するといった作業を行っていました。

PCIデバイスでは、ターゲット側がconfiguration spaceを用意することで、デバイスの素性や要求リソースを検出する仕組みが用意されています。したがって、Devitetreeはこれらのターゲットデバイスの定義を含めないこととしています（例外として、ソフト的にproveできないPCI host bridge deviceを挙げています）。

Devicetree format（概要編）

Devicetree Specificationに詳細な記述仕様があります。ざっと要点を抜粋していきます。

tree状に定義する様式となっており、'/'をルートノードとして、ファイルシステムのディレクトリ階層のように記述していきます。簡単な記述例を以下に示します。実用的な記述ではありませんが、コンパイルは通ります。

/dts-v1/;
/ {
        #address-cells = <1>;
        #size-cells = <1>;

        soc {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                intc: intc@100 {
                        reg = <1000 100>;
                };
                spi: spi@0 {
                        reg = <0 0>;
                        interrupts = <&intc 1>;
                };
    };
};

ここで soc や intc@100 はノードといいます。中括弧で括った要素（プロパティ）をまとめる器です。これはバスを表現したり、特定の機能をもつIPコアを表現したり、Flash memoryやセンサICを表現したりします。

また、ノードは何段でも階層化した記述ができ、CPUから見えるシステムバスの多段表現や、その先にあるIPコアのレジスタインタフェースを表現することができます。SoC内部に限らず、SPI・I2C・非同期バスなどを介して接続するデバイスを表現します。

それぞれのノードに、プロパティを定義します。プロパティは 項目名と値とからなる組み合わせで、値がないものも存在します。値はDTspecで規定されているものなら自由に設定できますが、それを参照するのは対応するドライバです。ドライバが判るように設定してあげる必要があります。

kernel versionが新しくなるにつれ、ドキュメントも整備されていきました。kernel/Documentation/devicetree/bindings/ 配下に、ある程度まとめられています。善意の協力のもとで作られていますので、必ずしも欲しい情報が存在する／正しいとは限りません。

自分が商用向けで触ったりする場合には 可能な限りソースコードも参照することをおすすめします。

initとは

init=/etc/preinit

設定ファイル

/etc/inittab

# /etc/inittab
#
# Copyright (C) 2001 Erik Andersen <andersen@codepoet.org>
#
# Note: BusyBox init doesn't support runlevels.  The runlevels field is
# completely ignored by BusyBox init. If you want runlevels, use
# sysvinit.
#
# Format for each entry: <id>:<runlevels>:<action>:<process>
#
# id        == tty to run on, or empty for /dev/console
# runlevels == ignored
# action    == one of sysinit, respawn, askfirst, wait, and once
# process   == program to run

# Startup the system
::sysinit:/bin/mount -t proc proc /proc
::sysinit:/bin/mount -o remount,rw /
::sysinit:/bin/mkdir -p /dev/pts
::sysinit:/bin/mkdir -p /dev/shm
::sysinit:/bin/mount -a
::sysinit:/bin/hostname -F /etc/hostname
# now run any rc scripts
::sysinit:/etc/init.d/rcS

# Put a getty on the serial port
#ttyS0::respawn:/sbin/getty -L ttyS0 115200 vt100 # GENERIC_SERIAL

# Stuff to do for the 3-finger salute
#::ctrlaltdel:/sbin/reboot

# Stuff to do before rebooting
::shutdown:/etc/init.d/rcK
::shutdown:/sbin/swapoff -a
::shutdown:/bin/umount -a -r

システムの終了

//applet:IF_HALT(APPLET(halt, BB_DIR_SBIN, BB_SUID_DROP))
//applet:IF_HALT(APPLET_ODDNAME(poweroff, halt, BB_DIR_SBIN, BB_SUID_DROP, poweroff))
//applet:IF_HALT(APPLET_ODDNAME(reboot, halt, BB_DIR_SBIN, BB_SUID_DROP, reboot))

int halt_main(int argc UNUSED_PARAM, char **argv)
|
...
	sleep(0);
	write_wtmp();  // last.logを記録する
	sync();        // デフォルトはsync(2)を実行する.

	kill(1,SIGTERM)	// initに signalを飛ばす. -f付きなら reboot(2)で 0x01234567 を渡す..

		bb_signals(0
			+ (1 << SIGUSR1) /* halt */
			+ (1 << SIGTERM) /* reboot */
			+ (1 << SIGUSR2) /* poweroff */
			, halt_reboot_pwoff);

static void halt_reboot_pwoff(int sig)
{
	const char *m;
	unsigned rb;

	/* We may call run() and it unmasks signals,
	 * including the one masked inside this signal handler.
	 * Testcase which would start multiple reboot scripts:
	 *  while true; do reboot; done
	 * Preventing it:
	 */
	reset_sighandlers_and_unblock_sigs();
		// ハンドラをデフォルトに戻して, 有効化

	run_shutdown_and_kill_processes();
		// 後述. run_actrions(),全プロセスにSIGTERM, sync(2),sleep(1sec),SIGKILL,sync(2)

	m = "halt";
	rb = RB_HALT_SYSTEM;
	if (sig == SIGTERM) {
		m = "reboot";
		rb = RB_AUTOBOOT;
	} else if (sig == SIGUSR2) {
		m = "poweroff";
		rb = RB_POWER_OFF;
	}
	message(L_CONSOLE, "Requesting system %s", m);
	pause_and_low_level_reboot(rb);
		// 後述. sleep(1sec), vfork(2)した子で reboot(magic:0x1234567), 親(pid=1)はsleep forever.
	/* not reached */
}

static void run_shutdown_and_kill_processes(void)
{
	/* Run everything to be run at "shutdown".  This is done _prior_
	 * to killing everything, in case people wish to use scripts to
	 * shut things down gracefully... */
	run_actions(SHUTDOWN);

	message(L_CONSOLE | L_LOG, "The system is going down NOW!");

	/* Send signals to every process _except_ pid 1 */
	kill(-1, SIGTERM);
	message(L_CONSOLE | L_LOG, "Sent SIG%s to all processes", "TERM");
	sync();
	sleep(1);

	kill(-1, SIGKILL);
	message(L_CONSOLE, "Sent SIG%s to all processes", "KILL");
	sync();
	/*sleep(1); - callers take care about making a pause */
}

static void pause_and_low_level_reboot(unsigned magic)
{
	pid_t pid;

	/* Allow time for last message to reach serial console, etc */
	sleep(1);

	/* We have to fork here, since the kernel calls do_exit(EXIT_SUCCESS)
	 * in linux/kernel/sys.c, which can cause the machine to panic when
	 * the init process exits... */
	pid = vfork();
	if (pid == 0) { /* child */
		reboot(magic);
		_exit(EXIT_SUCCESS);
	}
	while (1)
		sleep(1);
}

libc

/* Call kernel with additional two arguments the syscall requires.  */
int
reboot (int howto)
{
  return INLINE_SYSCALL (reboot, 3, (int) 0xfee1dead, 672274793, howto);
}

/*
 * Magic values required to use _reboot() system call.
 */

#define LINUX_REBOOT_MAGIC1     0xfee1dead
#define LINUX_REBOOT_MAGIC2     672274793
#define LINUX_REBOOT_MAGIC2A    85072278
#define LINUX_REBOOT_MAGIC2B    369367448
#define LINUX_REBOOT_MAGIC2C    537993216

/*
 * Commands accepted by the _reboot() system call.
 *
 * RESTART     Restart system using default command and mode.
 * HALT        Stop OS and give system control to ROM monitor, if any.
 * CAD_ON      Ctrl-Alt-Del sequence causes RESTART command.
 * CAD_OFF     Ctrl-Alt-Del sequence sends SIGINT to init task.
 * POWER_OFF   Stop OS and remove all power from system, if possible.
 * RESTART2    Restart system using given command string.
 * SW_SUSPEND  Suspend system using software suspend if compiled in.
 * KEXEC       Restart system using a previously loaded Linux kernel
 */

#define LINUX_REBOOT_CMD_RESTART        0x01234567
#define LINUX_REBOOT_CMD_HALT           0xCDEF0123
#define LINUX_REBOOT_CMD_CAD_ON         0x89ABCDEF
#define LINUX_REBOOT_CMD_CAD_OFF        0x00000000
#define LINUX_REBOOT_CMD_POWER_OFF      0x4321FEDC
#define LINUX_REBOOT_CMD_RESTART2       0xA1B2C3D4
#define LINUX_REBOOT_CMD_SW_SUSPEND     0xD000FCE2
#define LINUX_REBOOT_CMD_KEXEC          0x45584543

kernel実装

/*
 * Reboot system call: for obvious reasons only root may call it,
 * and even root needs to set up some magic numbers in the registers
 * so that some mistake won't make this reboot the whole machine.
 * You can also set the meaning of the ctrl-alt-del-key here.
 *
 * reboot doesn't sync: do that yourself before calling this.
 */
SYSCALL_DEFINE4(reboot, int, magic1, int, magic2, unsigned int, cmd,
		void __user *, arg)

	mutex_lock(&reboot_mutex);
	switch (cmd) {
	case LINUX_REBOOT_CMD_RESTART:
		kernel_restart(NULL);
		break;
..
	mutex_unlock(&reboot_mutex);
	return ret;
}

/**
 *	kernel_restart - reboot the system
 *	@cmd: pointer to buffer containing command to execute for restart
 *		or %NULL
 *
 *	Shutdown everything and perform a clean reboot.
 *	This is not safe to call in interrupt context.
 */
void kernel_restart(char *cmd)
{
	kernel_restart_prepare(cmd);
	migrate_to_reboot_cpu();
	syscore_shutdown();		// syscore_ops_listを走査する
	if (!cmd)
		printk(KERN_EMERG "Restarting system.\n");
	else
		printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
	kmsg_dump(KMSG_DUMP_RESTART);
	machine_restart(cmd);
}
EXPORT_SYMBOL_GPL(kernel_restart);

void kernel_restart_prepare(char *cmd)
{
	blocking_notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
	system_state = SYSTEM_RESTART;
	usermodehelper_disable();		// timeout: 5sec
	device_shutdown();		// timeoutなし, devices_kset->list を走査する.
}

アーキテクチャ依存部: machine_restart()

void machine_restart(char *cmd)
{
	local_irq_disable();
	smp_send_stop();

	if (arm_pm_restart)
		arm_pm_restart(reboot_mode, cmd);
	else
		do_kernel_restart(cmd);

	/* Give a grace period for failure to restart of 1s */
	mdelay(1000);

	/* Whoops - the platform was unable to reboot. Tell the user! */
	printk("Reboot failed -- System halted\n");
	local_irq_disable();
	while (1);
}

/*
 * Restart requires that the secondary CPUs stop performing any activity
 * while the primary CPU resets the system. Systems with multiple CPUs must
 * provide a HW restart implementation, to ensure that all CPUs reset at once.
 * This is required so that any code running after reset on the primary CPU
 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
 * executing pre-reset code, and using RAM that the primary CPU's code wishes
 * to use. Implementing such co-ordination would be essentially impossible.
 */
void machine_restart(char *cmd)
{
	/* Disable interrupts first */
	local_irq_disable();
	smp_send_stop();

	/*
	 * UpdateCapsule() depends on the system being reset via
	 * ResetSystem().
	 */
	if (efi_enabled(EFI_RUNTIME_SERVICES))
		efi_reboot(reboot_mode, NULL);

	/* Now call the architecture specific reboot code. */
	if (arm_pm_restart)
		arm_pm_restart(reboot_mode, cmd);
	else
		do_kernel_restart(cmd);

	/*
	 * Whoops - the architecture was unable to reboot.
	 */
	printk("Reboot failed -- System halted\n");
	while (1);
}

/**
 *	do_kernel_restart - Execute kernel restart handler call chain
 *
 *	Calls functions registered with register_restart_handler.
 *
 *	Expected to be called from machine_restart as last step of the restart
 *	sequence.
 *
 *	Restarts the system immediately if a restart handler function has been
 *	registered. Otherwise does nothing.
 */
void do_kernel_restart(char *cmd)
{
	atomic_notifier_call_chain(&restart_handler_list, reboot_mode, cmd);
}

This contents is translated from following web page.
It is almost translated by translate.google.co.jp. But I modify them to understand for me, maybe.
I hope you reading and writing assembler code with ARM. Let's enjoy!

About this document

The GNU C compiler for ARM RISC processors offers, to embed assembly language code into C programs.
This cool feature may be used for manually optimizing time critical parts of the software or to use specific processor instruction, which are not available in the C language.

It's assumed, that you are familiar with writing ARM assembler programs, because this is not an ARM assembler programming tutorial.
It's not a C language tutorial either.

All samples had been tested with GCC version 4, but most of them should work with earlier versions too.

GCC asm statement

Let's start with a simple example.
The following statement may be included in your code like any other C statement.

/* NOP example */
asm("mov r0,r0");

It moves the contents of register r0 to register r0.
In other words, it doesn't do much more than nothing.
It is also known as a NOP (no operation) statement and is typically used for very short delays.

Stop! Before adding this example right away to your C code, keep on reading and learn, why this may not work as expected.

With inline assembly you can use the same assembler instruction mnemonics as you'd use for writing pure ARM assembly code.
And you can write more than one assembler instruction in a single inline asm statement.
To make it more readable, you can put each instruction on a separate line.

asm(
"mov     r0, r0\n\t"
"mov     r0, r0\n\t"
"mov     r0, r0\n\t"
"mov     r0, r0"
);

The special sequence of linefeed and tab characters will keep the assembler listing looking nice.
It may seem a bit odd for the first time, but that's the way the compiler creates its own assembler code while compiling C statements.

So far, the assembler instructions are much the same as they'd appear in pure assembly language programs.
However, registers and constants are specified in a different way, if they refer to C expressions.
The general form of an inline assembler statement is

asm(code : output operand list : input operand list : clobber list);

The connection between assembly language and C operands is provided by an optional second and third part of the asm statement, the list of output and input operands.
We will explain the third optional part, the list of clobbers, later.

The next example of rotating bits passes C variables to assembly language.
It takes the value of one integer variable, right rotates the bits by one and stores the result in a second integer variable.

/* Rotating bits example */
asm("mov %[result], %[value], ror #1" : [result] "=r" (y) : [value] "r" (x));

Each asm statement is divided by colons into up to four parts:

1.The assembler instructions, defined in a single string literal:

"mov %[result], %[value], ror #1"

An optional list of output operands, separated by commas.
Each entry consists of a symbolic name enclosed in square brackets, followed by a constraint string, followed by a C expression enclosed in parentheses.
Our example uses just one entry:

[result] "=r" (y)

A comma separated list of input operands, which uses the same syntax as the list of output operands.
Again, this is optional and our example uses one operand only:

[value] "r" (x)

Optional list of clobbered registers, omitted in our example.

As shown in the initial NOP example, trailing parts of the asm statement may be omitted, if unused.
Inline asm statements containing assembler instruction only are also known as basic inline assembly, while statements containing optional parts are called extended inline assembly.
If an unused part is followed by one which is used, it must be left empty.
The following example sets the current program status register of the ARM CPU.
It uses an input, but no output operand.

asm("msr cpsr,%[ps]" : : [ps]"r"(status));

Even the code part may be left empty, though an empty string is required.
The next statement creates a special clobber to tell the compiler, that memory contents may have changed.
Again, the clobber list will be explained later, when we take a look to code optimization.

asm("":::"memory");

You can insert spaces, newlines and even C comments to increase readability.

In the code section, operands are referenced by a percent sign followed by the related symbolic name enclosed in square brackets.
It refers to the entry in one of the operand lists that contains the same symbolic name.
From the rotating bits example:
%[result] refers to output operand, the C variable y, and

%[value] refers to the input operand, the C variable x.

Symbolic operand names use a separate name space.
That means, that there is no relation to any other symbol table.
To put it simple: You can choose a name without taking care whether the same name already exists in your C code.
However, unique symbols must be used within each asm statement.

If you already looked to some working inline assembler statements written by other authors, you may have noticed a significant difference.
In fact, the GCC compiler supports symbolic names since version 3.1. For earlier releases the rotating bit example must be written as

asm("mov %0, %1, ror #1" : "=r" (result) : "r" (value));

Operands are referenced by a percent sign followed by a single digit, where %0 refers to the first %1 to the second operand and so forth.
This format is still supported by the latest GCC releases, but quite error-prone and difficult to maintain.
Imagine, that you have written a large number of assembler instructions, where operands have to be renumbered manually after inserting a new output operand.

If all this stuff still looks a little odd, don't worry.
Beside the mysterious clobber list, you have the strong feeling that something else is missing, right? Indeed, we didn't talk about the constraint strings in the operand lists.
I'd like to ask for your patience.
There's something more important to highlight in the next chapter.

C code optimization

There are two possible reasons why you want to use assembly language.
First is, that C is limited when we are getting closer to the hardware.
E.g. there's no C statement for directly modifying the processor status register.
The second reason is to create highly optimized code.
No doubt, the GNU C code optimizer does a good job, but the results are far away from handcrafted assembler code.

The subject of the chapter is often overlooked: When adding assembly language code by using inline assembler statements, this code is also processed by the C compiler's code optimizer.
Let's examine the part of a compiler listing which may have been generated from our rotating bits example:

00309DE5    ldr   r3, [sp, #0]    @ x, x
E330A0E1    mov   r3, r3, ror #1  @ tmp, x
04308DE5    str   r3, [sp, #4]    @ tmp, y

The compiler selected register r3 for bit rotation.
It could have selected any other register or two registers, one for each C variable.
It may not explicitly load the value or store the result.
Here is another listing, generated by a different compiler version with different compile options:

E420A0E1    mov r2, r4, ror #1    @ y, x

The compiler selected a unique register for each operand, using the value already cached in r4 and passing the result to the following code in r2.
Did you get the picture?

Often it becomes worse.
The compiler may even decide not to include your assembler code at all.
These decisions are part of the compiler's optimization strategy and depend on the context in which your assembler instructions are used.
For example, if you never use any of the output operands in the remaining part of the C program, the optimizer will most likely remove your inline assembler statement.
The NOP example we presented initially may be such a candidate as well, because to the compiler this is useless overhead, slowing down program execution.

The solution is to add the volatile attribute to the asm statement to instruct the compiler to exclude your assembler code from code optimization.
Remember, that you have been warned to use the initial example.
Here is the revised version:

/* NOP example, revised */
asm volatile("mov r0, r0");

But there is more trouble waiting for us.
A sophisticated optimizer will re-arrange the code.
The following C snippet had been left over after several last minute changes:

i++;
if (j == 1)
    x += 3;
i++;

The optimizer will recognize, that the two increments do not have any impact on the conditional statement.
Furthermore it knows, that incrementing a value by 2 will cost one ARM instruction only.
Thus, it will re-arrange the code to

if (j == 1)
    x += 3;
i += 2;

and save one ARM instruction.
As a result: There is no guarantee, that the compiled code will retain the sequence of statements given in the source code.

This may have a great impact on your code, as we will demonstrate now.
The following code intends to multiply c with b, of which one or both may be modified by an interrupt routine.
Disabling interrupts before accessing the variables and re-enable them afterwards looks like a good idea.

asm volatile("mrs r12, cpsr\n\t"
    "orr r12, r12, #0xC0\n\t"
    "msr cpsr_c, r12\n\t" ::: "r12", "cc");
c *= b; /* This may fail. */
asm volatile("mrs r12, cpsr\n"
    "bic r12, r12, #0xC0\n"
    "msr cpsr_c, r12" ::: "r12", "cc");

Unfortunately the optimizer may decide to do the multiplication first and then execute both inline assembler instructions or vice versa.
This will make our assembly code useless.

We can solve this with the help of the clobber list, which will be explained now.
The clobber list from the example above

"r12", "cc"

informs the compiler that the assembly code modifies register r12 and updates the condition code flags.
Btw. using a hard coded register will typically prevent best optimization results.
In general you should pass a variable and let the compiler choose the adequate register.
Beside register names and cc for the condition register, memory is a valid keyword too.
It tells the compiler that the assembler instruction may change memory locations.
This forces the compiler to store all cached values before and reload them after executing the assembler instructions.
And it must retain the sequence, because the contents of all variables is unpredictable after executing an asm statement with a memory clobber.

asm volatile("mrs r12, cpsr\n\t"
    "orr r12, r12, #0xC0\n\t"
    "msr cpsr_c, r12\n\t" :: : "r12", "cc", "memory");
c *= b; /* This is safe. */
asm volatile("mrs r12, cpsr\n"
    "bic r12, r12, #0xC0\n"
    "msr cpsr_c, r12" ::: "r12", "cc", "memory");

Invalidating all cached values may be suboptimal.
Alternatively you can add a dummy operand to create an artificial dependency:

asm volatile("mrs r12, cpsr\n\t"
    "orr r12, r12, #0xC0\n\t"
    "msr cpsr_c, r12\n\t" : "=X" (b) :: "r12", "cc");
c *= b; /* This is safe. */
asm volatile("mrs r12, cpsr\n"
    "bic r12, r12, #0xC0\n"
    "msr cpsr_c, r12" :: "X" (c) : "r12", "cc");

This code pretends to modify variable b in the first asm statement and to use the contents variable c in the second.
This will preserve the sequence of our three statements without invalidating other cached variables.

It is essential to understand how the optimizer affects inline assembler statements.
If something remains nebulous, better re-read this part before moving on the the next topic.

Input and output operands

We learned, that each input and output operand is described by a symbolic name enclosed in square bracket,
followed by a constraint string, which in turn is followed by a C expression in parentheses.

What are these constraints and why do we need them?
You probably know that every assembly instruction accepts specific operand types only.
For example, the branch instruction expects a target address to jump at.
However, not every memory address is valid, because the final opcode accepts a 24-bit offset only.
In contrary, the branch and exchange instruction expects a register that contains a 32-bit target address.
In both cases the operand passed from C to the inline assembler may be the same C function pointer.
Thus, when passing constants, pointers or variables to inline assembly statements, the inline assembler must know, how they should be represented in the assembly code.

For ARM processors, GCC 4 provides the following constraints.

Constraint characters may be prepended by a single constraint modifier.
Constraints without a modifier specify read-only operands.
Modifiers are:

Output operands must be write-only and the C expression result must be an lvalue, which means that the operands must be valid on the left side of assignments.
The C compiler is able to check this.

Input operands are, you guessed it, read-only.
Note, that the C compiler will not be able to check, whether the operands are of reasonable type for the kind of operation used in the assembler instructions.
Most problems will be detected during the late assembly stage, which is well known for its weird error messages.
Even if it claims to have found an internal compiler problem that should be immediately reported to the authors, you better check your inline assembler code first.

A strict rule is: Never ever write to an input operand.
But what, if you need the same operand for input and output?
The constraint modifier + does the trick as shown in the next example:

asm("mov %[value], %[value], ror #1" : [value] "+r" (y));

This is similar to our rotating bits example presented above.
It rotates the contents of the variable value to the right by one bit.
In opposite to the previous example, the result is not stored in another variable.
Instead the original contents of input variable will be modified.

The modifier + may not be supported by earlier releases of the compiler.
Luckily they offer another solution, which still works with the latest compiler version.
For input operators it is possible to use a single digit in the constraint string.
Using digit n tells the compiler to use the same register as for the n-th operand, starting with zero.
Here is an example:

asm("mov %0, %0, ror #1" : "=r" (value) : "0" (value));

Constraint "0" tells the compiler, to use the same input register that is used for the first output operand.

Note however, that this doesn't automatically imply the reverse case.
The compiler may choose the same registers for input and output, even if not told to do so.
You may remember the first assembly listing of the rotating bits example with two variables, where the compiler used the same register r3 for both variables.
The asm statement

asm("mov %[result],%[value],ror #1":[result] "=r" (y):[value] "r" (x));

00309DE5    ldr   r3, [sp, #0]    @ x, x
E330A0E1    mov   r3, r3, ror #1  @ tmp, x
04308DE5    str   r3, [sp, #4]    @ tmp, y

This is not a problem in most cases, but may be fatal if the output operator is modified by the assembler code before the input operator is used.
In situations where your code depends on different registers used for input and output operands, you must add the & constraint modifier to your output operand.
The following code demonstrates this problem.

asm volatile("ldr %0, [%1]"     "\n\t"
             "str %2, [%1, #4]" "\n\t"
             : "=&r" (rdv)
             : "r" (&table), "r" (wdv)
             : "memory");

A value is read from a table and then another value is written to another location in this table.
If the compiler would have chosen the same register for input and output, then the output value would have been destroyed on the first assembler instruction.
Fortunately, the & modifier instructs the compiler not to select any register for the output value, which is used for any of the input operands.

More recipes

Inline assembler as preprocessor macro（プリプロセッサマクロとしてのインラインアセンブラ）

In order to reuse your assembler language parts, it is useful to define them as macros and put them into include files.
Using such include files may produce compiler warnings, if they are used in modules, which are compiled in strict ANSI mode.
To avoid that, you can write __asm__ instead of asm and __volatile__ instead of volatile.
These are equivalent aliases.

Here is a macro which will convert a long value from little endian to big endian or vice versa:

#define BYTESWAP(val) \
    __asm__ __volatile__ ( \
        "eor     r3, %1, %1, ror #16\n\t" \
        "bic     r3, r3, #0x00FF0000\n\t" \
        "mov     %0, %1, ror #8\n\t" \
        "eor     %0, %0, r3, lsr #8" \
        : "=r" (val) \
        : "0"(val) \
        : "r3", "cc" \
    );

C stub functions

Macro definitions will include the same assembler code whenever they are referenced.
This may not be acceptable for larger routines.
In this case you may define a C stub function.

Here is the byte swap procedure again, this time implemented as a C function.

unsigned long ByteSwap(unsigned long val)
{
asm volatile (
        "eor     r3, %1, %1, ror #16\n\t"
        "bic     r3, r3, #0x00FF0000\n\t"
        "mov     %0, %1, ror #8\n\t"
        "eor     %0, %0, r3, lsr #8"
        : "=r" (val)
        : "0"(val)
        : "r3"
);
return val;
}

Replacing symbolic names of C variables（Cの変数をシンボリックに置換する）

By default GCC uses the same symbolic names of functions or variables in C and assembler code.
You can specify a different name for the assembler code by using a special form of the asm statement:

unsigned long value asm("clock") = 3686400;

This statement instructs the compiler to use the symbolic name clock rather than value.
This makes sense only for global variables.
Local variables (aka auto variables) do not have symbolic names in assembler code.

Replacing symbolic names of C functions
In order to change the name of a function, you need a prototype declaration, because the compiler will not accept the asm keyword in the function definition:

extern long Calc(void) asm ("CALCULATE");

Calling the function Calc() will create assembler instructions to call the function CALCULATE.

Forcing usage of specific registers（指定レジスタの使用を強制する）

A local variable may be held in a register.
You can instruct the inline assembler to use a specific register for it.

void Count(void) {
register unsigned char counter asm("r3");

... some code...
asm volatile("eor r3, r3, r3" : "=l" (counter));
... more code...
}

The assembler instruction, "eor r3, r3, r3", will clear the variable counter.
Be warned, that this sample is bad in most situations, because it interferes with the compiler's optimizer.
Furthermore, GCC will not completely reserve the specified register.
If the optimizer recognizes that the variable will not be referenced any longer, the register may be re-used.
But the compiler is not able to check whether this register usage conflicts with any predefined register.
If you reserve too many registers in this way, the compiler may even run out of registers during code generation.

Using registers temporarily

If you are using registers, which had not been passed as operands, you need to inform the compiler about this.
The following code will adjust a value to a multiple of four.
It uses r3 as a scratch register and lets the compiler know about this by specifying r3 in the clobber list.
Furthermore the CPU status flags are modified by the ands instruction and thus cc had been added to the clobbers.

asm volatile(
    "ands    r3, %1, #3"     "\n\t"
    "eor     %0, %0, r3" "\n\t"
    "addne   %0, #4"
    : "=r" (len)
    : "0" (len)
    : "cc", "r3"
  );

Again, hard coding register usage is always bad coding style.
Better implement a C stub function and use a local variable for temporary values.

Using constants（定数を使う）

You can use the mov instruction to load an immediate constant value into a register.
Basically, this is limited to values ranging from 0 to 255.

asm("mov r0, %[flag]" : : [flag] "I" (0x80));

But also larger values can be used when rotating the given range by an even number of bits.
In other words, any result of

n * 2^x

with n is in the mentioned range of 0 to 255 and x is an even number in the range of 0 to 24.
Because of rotation, x may be set to 26, 28 or 30, in which case bits 37 to 32 are folded to bits 5 to 0 resp.
Last not least, the binary complement of these values may be given, when using mvn instead of mov.

Sometimes you need to jump to a fixed memory address, which may be defined by a preprocessor macro.
You can use the following assembly code:

    ldr  r3, =JMPADDR
    bx   r3

This will work with any legal address value.
If the constant fits (for example 0x20000000), then the smart assembler will convert this to

    mov  r3, #0x20000000
    bx   r3

If it doesn't fit (for example 0x00F000F0), then the assembler will load the value from the literal pool.

    ldr  r3, .L1
    bx   r3
    ...
    .L1: .word 0x00F000F0

With inline assembly it works in the same way.
But instead of using ldr, you can simply provide a constant as a register value:

asm volatile("bx %0" : : "r" (JMPADDR));

Depending on the actual value of the constant, either mov, ldr or any of its variants is used.
If JMPADDR is defined as 0xFFFFFF00, then the resulting code will be similar to

    mvn  r3, #0xFF
    bx   r3

The real world is more complicated.
It may happen, that we need to load a specific register with a constant.
Let's assume, that we want to call a subroutine, but we want to return to another address than the one that follows our branch.
This is can be useful when embedded firmware returns from main.
In this case we need to load the link register. Here is the assembly code:

    ldr  lr, =JMPADDR
    ldr  r3, main
    bx   r3

Any idea how to implement this in inline assembly? Here is a solution:

asm volatile(
    "mov lr, %1\n\t"
    "bx %0\n\t"
    : : "r" (main), "I" (JMPADDR));

But there is still a problem.
We use mov here and this will work as long as the value of JMPADDR fits.
The resulting code will be the same than what we get in pure assembly code.
If it doesn't fit, then we need ldr instead.
But unfortunately there is no way to express in inline assembly.

    ldr  lr, =JMPADDR

Instead, we must write

asm volatile(
    "mov lr, %1\n\t"
    "bx %0\n\t"
    : : "r" (main), "r" (JMPADDR));

Compared to the pure assembly code, we end up with an additional statement, using an additional register.

    ldr     r3, .L1
    ldr     r2, .L2
    mov     lr, r2
    bx      r3

Register Usage（レジスタの使い方）

It is always a good idea to analyze the assembly listing output of the C compiler and study the generated code.
The following table of the compiler's typical register usage will be probably helpful to understand the code.

Common pitfalls

Instruction sequence

Developers often expect, that a sequence of instructions remains in the final code as specified in the source code.
This assumption is wrong and often introduces hard to find bugs.
Actually, asm statements are processed by the optimizer in the same way as other C statements.
They may be rearranged if dependencies allow this.

The chapter "C code optimization" discusses the details and offers solutions.

Defining a variable as a specific register

Even if a variable had been forcibly assigned to a specific register, the resulting code may not work as expected.
Consider the following snippet:

int foo(int n1, int n2) {
  register int n3 asm("r7") = n2;
  asm("mov r7, #4");
  return n3;
}

The compiler is instructed to use r7 as a local variable n3, which is initialized by parameter n2.
Then the inlined assembly statement sets r7 to 4, which should be finally returned.
However, this may go completely wrong.
Remember, that compiler cannot recognize, what's happening inside the inline assembly.
But the optimizer is smart on the C code, generating the following assembly code.

foo:
  mov r7, #4
  mov r0, r1
  bx  lr

Instead of returning r7, the value of n2 is returned, which had been passed to our function in r1.
What happed here? Well, while the final code still contains our inline assembly statement, the C code optimizer decided, that n3 is not required.
It directly returns parameter n2 instead.

Just assigning a variable to a fixed register does not mean, that the C compiler will use that variable.
We still have to tell the compiler, that a variable is modified inside the inline assembly operation.
For the given example, we need to extend the asm statement with an output operator:

asm("mov %0, #4" : "=l" (n3));

Now the C compiler is aware, that n3 is modified and will generate the expected result:

foo:
  push {r7, lr}
  mov  r7, #4
  mov  r0, r7
  pop  {r7, pc}

Executing in Thumb status

Be aware, that, depending on the given compile options, the compiler may switch to thumb state.
Using inline assembler with instructions that are not available in thumb state will result in cryptic compile errors.

Assembly code size

In most cases the compiler will correctly determine the size of the assembler instruction, but it may become confused by assembler macros.
Better avoid them.

In case you are confused: This is about assembly language macros, not C preprocessor macros.
It is fine to use the latter.

Labels

Within the assembler instruction you can use labels as jump targets.
However, you must not jump from one assembler instruction into another.
The optimizer knows nothing about those branches and may generate bad code.

Preprocessor macros

Inline assembly instruction cannot contain preprocessor macros, because for the preprocessor these instruction are nothing else but string constants.

If your assembly code must refer to values that are defined by macros, see the chapter about "Using constants" above.

External links

For a more thorough discussion of inline assembly usage, see the gcc user manual.
The latest version of the gcc manual is always available here:
http://gcc.gnu.org/onlinedocs/

Copyright

Copyright (C) 2007-2013 by Harald Kipp.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
or any later version published by the Free Software Foundation.

Document History

Advent calender2015

今年も書かせていただくことにしました。比較的まともに？記事を書くことのできるトリガーとして助かります。

Linux kernel vanilla v4.2

本記事では、著者の技量の都合により語彙が適当では無いことがあります。指摘いただけますと助かります。

procfsで見えるもの

稼働しているシステムで動いているプロセスを調べるために、psコマンドを使っていますよね。busybox版のソースコードを見ると判りやすいのですが、/proc配下のファイルを参照して情報を集めているのです。/procは、procfsがマウントされており、物理記憶装置上のファイルシステムではなく、Linux kernelとユーザランドとをつないでいるインタフェースでもあります。

タスク情報

ユーザランドでは、プロセス、スレッドと区別していますが、kernelではいずれも"task struct"で管理されます。スレッドは、libc実装ではプロセス空間を共有するtaskと考えるとよいでしょう。forkするときは注意が必要なのですが、これはまた別の機会があればそちらで。。。

本題のプロセス情報、以下のディレクトリ配下にあるファイルから取得ができます。

/proc/<id>/

このファイルを通して読み書きされるコードは、procfsのところでも触れたとおり、kernelのフレームワークを利用すると簡潔なコードになります。とりあえずソースコードを見てみましょう：

FILE: fs/proc/base.c

static const struct pid_entry tid_base_stuff[] = {
	ONE("stat",      S_IRUGO, proc_tid_stat),
	ONE("statm",     S_IRUGO, proc_pid_statm),
	REG("maps",      S_IRUGO, proc_tid_maps_operations),

statにpsで表示するための情報がたくさん含まれているようです（busybox版psコマンドソースコードより）：

int proc_tid_stat(struct seq_file *m, struct pid_namespace *ns,
			struct pid *pid, struct task_struct *task)
{
	return do_task_stat(m, ns, pid, task, 0);
}

FILE: fs/proc/array.c

static int do_task_stat(struct seq_file *m, struct pid_namespace *ns,
			struct pid *pid, struct task_struct *task, int whole)

ここをざーっと眺めていくと、なにを表示しているのかがわかりますね！（ブン投げ

/proc/PID/statの表示コード（変数はこの手前に代入されている）

	seq_printf(m, "%d (%s) %c", pid_nr_ns(pid, ns), tcomm, state);
	seq_put_decimal_ll(m, ' ', ppid);
	seq_put_decimal_ll(m, ' ', pgid);
	seq_put_decimal_ll(m, ' ', sid);
	seq_put_decimal_ll(m, ' ', tty_nr);
	seq_put_decimal_ll(m, ' ', tty_pgrp);
	seq_put_decimal_ull(m, ' ', task->flags);
	seq_put_decimal_ull(m, ' ', min_flt);
	seq_put_decimal_ull(m, ' ', cmin_flt);
	seq_put_decimal_ull(m, ' ', maj_flt);
	seq_put_decimal_ull(m, ' ', cmaj_flt);
	seq_put_decimal_ull(m, ' ', cputime_to_clock_t(utime));
	seq_put_decimal_ull(m, ' ', cputime_to_clock_t(stime));
	seq_put_decimal_ll(m, ' ', cputime_to_clock_t(cutime));
	seq_put_decimal_ll(m, ' ', cputime_to_clock_t(cstime));
	seq_put_decimal_ll(m, ' ', priority);
	seq_put_decimal_ll(m, ' ', nice);
	seq_put_decimal_ll(m, ' ', num_threads);
	seq_put_decimal_ull(m, ' ', 0);
	seq_put_decimal_ull(m, ' ', start_time);
	seq_put_decimal_ull(m, ' ', vsize);
	seq_put_decimal_ull(m, ' ', mm ? get_mm_rss(mm) : 0);
	seq_put_decimal_ull(m, ' ', rsslim);
	seq_put_decimal_ull(m, ' ', mm ? (permitted ? mm->start_code : 1) : 0);
	seq_put_decimal_ull(m, ' ', mm ? (permitted ? mm->end_code : 1) : 0);
	seq_put_decimal_ull(m, ' ', (permitted && mm) ? mm->start_stack : 0);
	seq_put_decimal_ull(m, ' ', esp);
	seq_put_decimal_ull(m, ' ', eip);
	/* The signal information here is obsolete.
	 * It must be decimal for Linux 2.0 compatibility.
	 * Use /proc/#/status for real-time signals.
	 */
	seq_put_decimal_ull(m, ' ', task->pending.signal.sig[0] & 0x7fffffffUL);
	seq_put_decimal_ull(m, ' ', task->blocked.sig[0] & 0x7fffffffUL);
	seq_put_decimal_ull(m, ' ', sigign.sig[0] & 0x7fffffffUL);
	seq_put_decimal_ull(m, ' ', sigcatch.sig[0] & 0x7fffffffUL);
	seq_put_decimal_ull(m, ' ', wchan);
	seq_put_decimal_ull(m, ' ', 0);
	seq_put_decimal_ull(m, ' ', 0);
	seq_put_decimal_ll(m, ' ', task->exit_signal);
	seq_put_decimal_ll(m, ' ', task_cpu(task));
	seq_put_decimal_ull(m, ' ', task->rt_priority);
	seq_put_decimal_ull(m, ' ', task->policy);
	seq_put_decimal_ull(m, ' ', delayacct_blkio_ticks(task));
	seq_put_decimal_ull(m, ' ', cputime_to_clock_t(gtime));
	seq_put_decimal_ll(m, ' ', cputime_to_clock_t(cgtime));

	if (mm && permitted) {
		seq_put_decimal_ull(m, ' ', mm->start_data);
		seq_put_decimal_ull(m, ' ', mm->end_data);
		seq_put_decimal_ull(m, ' ', mm->start_brk);
		seq_put_decimal_ull(m, ' ', mm->arg_start);
		seq_put_decimal_ull(m, ' ', mm->arg_end);
		seq_put_decimal_ull(m, ' ', mm->env_start);
		seq_put_decimal_ull(m, ' ', mm->env_end);
	} else
		seq_printf(m, " 0 0 0 0 0 0 0");

	if (permitted)
		seq_put_decimal_ll(m, ' ', task->exit_code);
	else
		seq_put_decimal_ll(m, ' ', 0);

	seq_putc(m, '\n');
	if (mm)
		mmput(mm);

pid_nr_ns()では、namespaceで管理しているpidに変換する関数のようです。namespaceも、不勉強なため説明できるような理解はできていません。

ぼちぼち調べながら見ていきましょう... schedulerが参照するようなcpu timeとかあるので、ここだけ見ても意味は理解できない雰囲気ですね。

コメントも面白いですね。RT-signalは statusを見ろって書いてます。

	/* The signal information here is obsolete.
	 * It must be decimal for Linux 2.0 compatibility.
	 * Use /proc/#/status for real-time signals.
	 */

※per proces flags

/*
 * Per process flags
 */
#define PF_EXITING	0x00000004	/* getting shut down */
#define PF_EXITPIDONE	0x00000008	/* pi exit done on shut down */
#define PF_VCPU		0x00000010	/* I'm a virtual CPU */
#define PF_WQ_WORKER	0x00000020	/* I'm a workqueue worker */
#define PF_FORKNOEXEC	0x00000040	/* forked but didn't exec */
#define PF_MCE_PROCESS  0x00000080      /* process policy on mce errors */
#define PF_SUPERPRIV	0x00000100	/* used super-user privileges */
#define PF_DUMPCORE	0x00000200	/* dumped core */
#define PF_SIGNALED	0x00000400	/* killed by a signal */
#define PF_MEMALLOC	0x00000800	/* Allocating memory */
#define PF_NPROC_EXCEEDED 0x00001000	/* set_user noticed that RLIMIT_NPROC was exceeded */
#define PF_USED_MATH	0x00002000	/* if unset the fpu must be initialized before use */
#define PF_USED_ASYNC	0x00004000	/* used async_schedule*(), used by module init */
#define PF_NOFREEZE	0x00008000	/* this thread should not be frozen */
#define PF_FROZEN	0x00010000	/* frozen for system suspend */
#define PF_FSTRANS	0x00020000	/* inside a filesystem transaction */
#define PF_KSWAPD	0x00040000	/* I am kswapd */
#define PF_MEMALLOC_NOIO 0x00080000	/* Allocating memory without IO involved */
#define PF_LESS_THROTTLE 0x00100000	/* Throttle me less: I clean memory */
#define PF_KTHREAD	0x00200000	/* I am a kernel thread */
#define PF_RANDOMIZE	0x00400000	/* randomize virtual address space */
#define PF_SWAPWRITE	0x00800000	/* Allowed to write to swap */
#define PF_NO_SETAFFINITY 0x04000000	/* Userland is not allowed to meddle with cpus_allowed */
#define PF_MCE_EARLY    0x08000000      /* Early kill for mce process policy */
#define PF_MUTEX_TESTER	0x20000000	/* Thread belongs to the rt mutex tester */
#define PF_FREEZER_SKIP	0x40000000	/* Freezer should not count it as freezable */
#define PF_SUSPEND_TASK 0x80000000      /* this thread called freeze_processes and should not be frozen */

cmin_fltとかの説明。統計情報ですね...

		/*
		 * The resource counters for the group leader are in its
		 * own task_struct.  Those for dead threads in the group
		 * are in its signal_struct, as are those for the child
		 * processes it has previously reaped.  All these
		 * accumulate in the parent's signal_struct c* fields.
		 *
		 * We don't bother to take a lock here to protect these
		 * p->signal fields because the whole thread group is dead
		 * and nobody can change them.
		 *
		 * psig->stats_lock also protects us from our sub-theads
		 * which can reap other children at the same time. Until
		 * we change k_getrusage()-like users to rely on this lock
		 * we have to take ->siglock as well.
		 *
		 * We use thread_group_cputime_adjusted() to get times for
		 * the thread group, which consolidates times for all threads
		 * in the group including the group leader.
		 */

prio : RT[0..99], user [100..140], 120がnice=0, user-nice = -20..+19 => 100..139

とりあえずここまで。。。本当はpsコマンドでタスク状態をモニタして、不具合や性能問題の追跡例を書いてみようかと思っていました。それよりも、ユーザランドからプロセスの状態を見る方法を示したほうが応用範囲が広がるだろうと思われます。

一部未確認がありますが、年内には更新を終わらせたいと思います。。。

5. Ring Library

The ring allows the management of queues. Instead of having a linked list of infinite size, the rte_ring has the following properties:

• FIFO
• Maximum size is fixed, the pointers are stored in a table
• Lockless implementation
• Multi-consumer or single-consumer dequeue
• Multi-producer or single-producer enqueue
• Bulk dequeue - Dequeues the specified count of objects if successful; otherwise fails
• Bulk enqueue - Enqueues the specified count of objects if successful; otherwise fails
• Burst dequeue - Dequeue the maximum available objects if the specified count cannot be fulfilled
• Burst enqueue - Enqueue the maximum available objects if the specified count cannot be fulfilled

The advantages of this data structure over a linked list queue are as follows:

• Faster; only requires a single Compare-And-Swap instruction of sizeof(void *) instead of several double-Compare-And-Swap instructions.
• Simpler than a full lockless queue.
• Adapted to bulk enqueue/dequeue operations. As pointers are stored in a table, a dequeue of several objects will not produce as many cache misses as in a linked queue. Also, a bulk dequeue of many objects does not cost more than a dequeue of a simple object.

• 早い. 複数の"double-Compare-And-Swap"に代わって、たった１つのsizeof(void*)を"Compare-And-Swap"する命令を必要とする
• 完全なロックレスキューよりも単純である
• バルクエンキュー・デキュー操作に対応。ポインタはテーブルに保存されるので、幾らかのオブジェクトのデキューでも、リンクドキューのように多くのキャッシュミスは発生しない。多くのオブジェクトのバルクデキューも、単純なオブジェクトのデキューよりもコストはかからない。

The disadvantages:

• Size is fixed
• Having many rings costs more in terms of memory than a linked list queue. An empty ring contains at least N pointers.

• サイズは固定
• リンクドリストキューよりも多くのメモリを必要とする。空のリングは少なくともN個のポインタから構成される。

A simplified representation of a Ring is shown in with consumer and producer head and tail pointers to objects stored in the data structure.

The following code was added in FreeBSD 8.0, and is used in some network device drivers (at least in Intel drivers):

bufring.h in FreeBSD
bufring.c in FreeBSD

The following is a link describing the Linux Lockless Ring Buffer Design.
http://lwn.net/Articles/340400/

5.3. Additional Features

5.3.1. Name

A ring is identified by a unique name.
It is not possible to create two rings with the same name (rte_ring_create() returns NULL if this is attempted).

5.3.2. Water Marking

The ring can have a high water mark (threshold).
Once an enqueue operation reaches the high water mark, the producer is notified, if the water mark is configured.
This mechanism can be used, for example, to exert a back pressure on I/O to inform the LAN to PAUSE.

5.3.3. Debug

When debug is enabled (CONFIG_RTE_LIBRTE_RING_DEBUG is set), the library stores some per-ring statistic counters about the number of enqueues/dequeues.
These statistics are per-core to avoid concurrent accesses or atomic operations.

5.4. Use Cases

Use cases for the Ring library include:

• Communication between applications in the DPDK
• Used by memory pool allocator

• DPDK内のアプリケーション間のコミュニケーション
• メモリプールアロケータでの使われ方

5.5. Anatomy of a Ring Buffer (リングバッファの解剖学)

This section explains how a ring buffer operates.
The ring structure is composed of two head and tail couples; one is used by producers and one is used by the consumers.
The figures of the following sections refer to them as prod_head, prod_tail, cons_head and cons_tail.

Each figure represents a simplified state of the ring, which is a circular buffer.
The content of the function local variables is represented on the top of the figure, and the content of ring structure is represented on the bottom of the figure.

5.5.1. Single Producer Enqueue

5.5.2. Single Consumer Dequeue

5.5.3. Multiple Producers Enqueue

5.5.4. Modulo 32-bit Indexes

5.6. References

• bufring.h in FreeBSD (version 8)\ http://svn.freebsd.org/viewvc/base/release/8.0.0/sys/sys/buf_ring.h?revision=199625&view=markup
• bufring.c in FreeBSD (version 8)\ http://svn.freebsd.org/viewvc/base/release/8.0.0/sys/kern/subr_bufring.c?revision=199625&view=markup
• Linux Lockless Ring Buffer Design\ http://lwn.net/Articles/340400/

7. Mbuf Library

The mbuf library provides the ability to allocate and free buffers (mbufs) that may be used by the DPDK application to store message buffers.
The message buffers are stored in a mempool, using the Mempool Library.

A rte_mbuf struct can carry network packet buffers or generic control buffers (indicated by the CTRL_MBUF_FLAG).
This can be extended to other types.
The rte_mbuf header structure is kept as small as possible and currently uses just two cache lines, with the most frequently used fields being on the first of the two cache lines.

7.1. Design of Packet Buffers

7.2. Buffers Stored in Memory Pools

7.3. Constructors

7.4. Allocating and Freeing mbufs

7.5. Manipulating mbufs

This library provides some functions for manipulating the data in a packet mbuf.
For instance:

• Get data length
• Get a pointer to the start of data
• Prepend data before data
• Append data after data
• Remove data at the beginning of the buffer (rte_pktmbuf_adj())
• Remove data at the end of the buffer (rte_pktmbuf_trim()) Refer to the DPDK API Reference for details.

• データ長
• 最初のデータへのポインタ取得
• データの前にデータを追加
• データの後ろにデータを追加
• バッファの最初のデータを削除 (rte_pktmbuf_adj())
• バッファの最後のデータを削除 (rte_pktmbuf_trim())

7.6. Meta Information

Some information is retrieved by the network driver and stored in an mbuf to make processing easier.
For instance, the VLAN, the RSS hash result (see Poll Mode Driver) and a flag indicating that the checksum was computed by hardware.

An mbuf also contains the input port (where it comes from), and the number of segment mbufs in the chain.

For chained buffers, only the first mbuf of the chain stores this meta information.

7.7. Direct and Indirect Buffers

A direct buffer is a buffer that is completely separate and self-contained.
An indirect buffer behaves like a direct buffer but for the fact that the buffer pointer and data offset in it refer to data in another direct buffer.
This is useful in situations where packets need to be duplicated or fragmented, since indirect buffers provide the means to reuse the same packet data across multiple buffers.

A buffer becomes indirect when it is “attached” to a direct buffer using the rte_pktmbuf_attach() function.
Each buffer has a reference counter field and whenever an indirect buffer is attached to the direct buffer, the reference counter on the direct buffer is incremented.
Similarly, whenever the indirect buffer is detached, the reference counter on the direct buffer is decremented.
If the resulting reference counter is equal to 0, the direct buffer is freed since it is no longer in use.

There are a few things to remember when dealing with indirect buffers.
First of all, it is not possible to attach an indirect buffer to another indirect buffer.
Secondly, for a buffer to become indirect, its reference counter must be equal to 1, that is, it must not be already referenced by another indirect buffer.
Finally, it is not possible to reattach an indirect buffer to the direct buffer (unless it is detached first).

While the attach/detach operations can be invoked directly using the recommended rte_pktmbuf_attach() and rte_pktmbuf_detach() functions, it is suggested to use the higher-level rte_pktmbuf_clone() function, which takes care of the correct initialization of an indirect buffer and can clone buffers with multiple segments.

Since indirect buffers are not supposed to actually hold any data, the memory pool for indirect buffers should be configured to indicate the reduced memory consumption.
Examples of the initialization of a memory pool for indirect buffers (as well as use case examples for indirect buffers) can be found in several of the sample applications, for example, the IPv4 Multicast sample application.

7.8. Debug

In debug mode (CONFIG_RTE_MBUF_DEBUG is enabled), the functions of the mbuf library perform sanity checks before any operation (such as, buffer corruption, bad type, and so on).

8. Poll Mode Driver

The DPDK includes 1 Gigabit, 10 Gigabit and 40 Gigabit and para virtualized virtio Poll Mode Drivers.

A Poll Mode Driver (PMD) consists of APIs, provided through the BSD driver running in user space, to configure the devices and their respective queues.
In addition, a PMD accesses the RX and TX descriptors directly without any interrupts (with the exception of Link Status Change interrupts) to quickly receive, process and deliver packets in the user's application.
This section describes the requirements of the PMDs, their global design principles and proposes a high-level architecture and a generic external API for the Ethernet PMDs.

8.1. Requirements and Assumptions（要件と前提）

The DPDK environment for packet processing applications allows for two models, run-to-completion and pipe-line:

• In the run-to-completion model, a specific port's RX descriptor ring is polled for packets through an API.

Packets are then processed on the same core and placed on a port's TX descriptor ring through an API for transmission.

• In the pipe-line model, one core polls one or more port's RX descriptor ring through an API.

Packets are received and passed to another core via a ring.
The other core continues to process the packet which then may be placed on a port's TX descriptor ring through an API for transmission.

• run-to-completionモデルでは、特定のポートのRXデスクリプタリングは、APIを介してパケットのためにポーリングされる。\ パケットは、同じコアに処理され、送信のためのAPIを介してポートのTXデスクリプタリング上に配置される。
• パイプラインモデルでは、一つのコアにポーリングつまたは複数のポートのRXデスクリプタリングAPIを介する。\ パケットは受信され、リングを介して別のコアに渡される。\ 他のコアは、送信のためのAPIを介してポートのTXデスクリプタリング上に配置することができるパケットの処理を続行します。

In a synchronous run-to-completion model, each logical core assigned to the DPDK executes a packet processing loop that includes the following steps:
-Retrieve input packets through the PMD receive API
-Process each received packet one at a time, up to its forwarding
-Send pending output packets through the PMD transmit API

• PMDの受信APIを介して、入力パケットを取得
• プロセスごとに、その転送まで、一度に入力パケットを受信
• PMD送信APIを介して、保留中の出力パケットを送信します

Conversely, in an asynchronous pipe-line model, some logical cores may be dedicated to the retrieval of received packets and other logical cores to the processing of previously received packets.
Received packets are exchanged between logical cores through rings. The loop for packet retrieval includes the following steps:
-Retrieve input packets through the PMD receive API
-Provide received packets to processing lcores through packet queues

• PMDの受信APIを介して、入力パケットを取得
• パケットキューを介して処理lcoresに受信したパケットを提供する

The loop for packet processing includes the following steps:
-Retrieve the received packet from the packet queue
-Process the received packet, up to its retransmission if forwarded

• パケットキューから受信したパケットを取得
• 転送された場合は、その再送信までの受信したパケットを処理する

To avoid any unnecessary interrupt processing overhead, the execution environment must not use any asynchronous notification mechanisms.
Whenever needed and appropriate, asynchronous communication should be introduced as much as possible through the use of rings.

Avoiding lock contention is a key issue in a multi-core environment.
To address this issue, PMDs are designed to work with per-core private resources as much as possible.
For example, a PMD maintains a separate transmit queue per-core, per-port.
In the same way, every receive queue of a port is assigned to and polled by a single logical core (lcore).

To comply with Non-Uniform Memory Access (NUMA), memory management is designed to assign to each logical core a private buffer pool in local memory to minimize remote memory access.
The configuration of packet buffer pools should take into account the underlying physical memory architecture in terms of DIMMS, channels and ranks.
The application must ensure that appropriate parameters are given at memory pool creation time. See Mempool Library.

8.2. Design Principles (設計原則)

The API and architecture of the Ethernet* PMDs are designed with the following guidelines in mind.

PMDs must help global policy-oriented decisions to be enforced at the upper application level.
Conversely, NIC PMD functions should not impede the benefits expected by upper-level global policies, or worse prevent such policies from being applied.

For instance, both the receive and transmit functions of a PMD have a maximum number of packets/descriptors to poll.
This allows a run-to-completion processing stack to statically fix or to dynamically adapt its overall behavior through different global loop policies, such as:
-Receive, process immediately and transmit packets one at a time in a piecemeal fashion.
-Receive as many packets as possible, then process all received packets, transmitting them immediately.
-Receive a given maximum number of packets, process the received packets, accumulate them and finally send all accumulated packets to transmit.

• 受信すると、直ちに処理して、断片的に同時にそのパケットを送信する
• できるだけ多くのパケットを受信し、すべての受信パケットを処理し、その後すぐにそれらを送信する
• 指定された最大数のパケットを受信、受信したパケットは処理され、それらを蓄積し、最終的に伝送するために、すべての蓄積されたパケットを送信する

To achieve optimal performance,
overall software design choices and pure software optimization techniques must be considered and balanced against available low-level hardware-based optimization features (CPU cache properties, bus speed, NIC PCI bandwidth, and so on).
The case of packet transmission is an example of this software/hardware tradeoff issue when optimizing burst-oriented network packet processing engines.
In the initial case, the PMD could export only an rte_eth_tx_one function to transmit one packet at a time on a given queue.
On top of that, one can easily build an rte_eth_tx_burst function that loops invoking the rte_eth_tx_one function to transmit several packets at a time.
However, an rte_eth_tx_burst function is effectively implemented by the PMD to minimize the driver-level transmit cost per packet through the following optimizations:

-Share among multiple packets the un-amortized cost of invoking the rte_eth_tx_one function.
-Enable the rte_eth_tx_burst function to take advantage of burst-oriented hardware features (prefetch data in cache, use of NIC head/tail registers)
to minimize the number of CPU cycles per packet,
for example by avoiding unnecessary read memory accesses to ring transmit descriptors,
or by systematically using arrays of pointers that exactly fit cache line boundaries and sizes.
-Apply burst-oriented software optimization techniques to remove operations that would otherwise be unavoidable, such as ring index wrap back management.

• 複数のパケットのうち、rte_eth_tx_one関数を呼び出すの未償却原価（呼び出しオーバヘッド？）
• rte_eth_tx_burst関数を有効にする。\パケットあたりのCPUサイクル数を最小化するため、バースト志向ハードウェア機能（キャッシュ内のプリフェッチデータや、NICヘッド／テールレジスタを使う）\たとえば、リング送信デスクリプタのメモリ読み込みアクセスを除去したり、キャッシュライン境界及びサイズに正確に適合（アライメント）したポインタアレイを使う。
• このようなリングインデックスバックラップ管理などの他の方法で避けられないだろうな操作を削除するには、バースト指向ソフトウェア最適化技術を適用します。

Burst-oriented functions are also introduced via the API for services that are intensively used by the PMD.
This applies in particular to buffer allocators used to populate NIC rings, which provide functions to allocate/free several buffers at a time.
For example, an mbuf_multiple_alloc function returning an array of pointers to rte_mbuf buffers which speeds up the receive poll function of the PMD when replenishing multiple descriptors of the receive ring.

8.3. Logical Cores, Memory and NIC Queues Relationships (論理コア、メモリ、NICキューの関係)¶

The DPDK supports NUMA allowing for better performance when a processor's logical cores and interfaces utilize its local memory.
Therefore, mbuf allocation associated with local PCIe* interfaces should be allocated from memory pools created in the local memory.
The buffers should, if possible, remain on the local processor to obtain the best performance results and RX and TX buffer descriptors should be populated with mbufs allocated from a mempool allocated from local memory.

The run-to-completion model also performs better if packet or data manipulation is in local memory instead of a remote processors memory.
This is also true for the pipe-line model provided all logical cores used are located on the same processor.

Multiple logical cores should never share receive or transmit queues for interfaces since this would require global locks and hinder performance.

8.4. Device Identification and Configuration （デバイスの識別と設定）

8.4.1. Device Identification（識別）

Each NIC port is uniquely designated by its (bus/bridge, device, function) PCI identifiers assigned by the PCI probing/enumeration function executed at DPDK initialization.
Based on their PCI identifier, NIC ports are assigned two other identifiers:
- A port index used to designate the NIC port in all functions exported by the PMD API.
- A port name used to designate the port in console messages, for administration or debugging purposes. For ease of use, the port name includes the port index.

• PMD APIによってエクスポートされたすべての関数でNICポートを指定するためのポートインデックス
• 管理またはデバッグの目的のために、コンソールメッセージでポートを指定するために使用されるポート名。使いやすさのために、ポート名、ポートインデックスを含む。

8.4.2. Device Configuration（設定）

The configuration of each NIC port includes the following operations:
- Allocate PCI resources
- Reset the hardware (issue a Global Reset) to a well-known default state
- Set up the PHY and the link
- Initialize statistics counters
The PMD API must also export functions to start/stop the all-multicast feature of a port and functions to set/unset the port in promiscuous mode.

• PCIリソースを割り当て
• よく知られているデフォルトの状態に（グローバルリセットを発行して）ハードウェアをリセット
• PHYとリンクを設定
• 統計カウンタを初期化

Some hardware offload features must be individually configured at port initialization through specific configuration parameters.
This is the case for the Receive Side Scaling (RSS) and Data Center Bridging (DCB) features for example.

8.4.3. On-the-Fly Configuration

All device features that can be started or stopped “on the fly” (that is, without stopping the device) do not require the PMD API to export dedicated functions for this purpose.

All that is required is the mapping address of the device PCI registers to implement the configuration of these features in specific functions outside of the drivers.

For this purpose, the PMD API exports a function that provides all the information associated with a device that can be used to set up a given device feature outside of the driver.
This includes the PCI vendor identifier, the PCI device identifier, the mapping address of the PCI device registers, and the name of the driver.

The main advantage of this approach is that it gives complete freedom on the choice of the API used to configure, to start, and to stop such features.

As an example, refer to the configuration of the IEEE1588 feature for the Intel® 82576 Gigabit Ethernet Controller and the Intel® 82599 10 Gigabit Ethernet Controller controllers in the testpmd application.

Other features such as the L3/L4 5-Tuple packet filtering feature of a port can be configured in the same way.
Ethernet* flow control (pause frame) can be configured on the individual port.
Refer to the testpmd source code for details.
Also, L4 (UDP/TCP/ SCTP) checksum offload by the NIC can be enabled for an individual packet as long as the packet mbuf is set up correctly.
In terms of UDP tunneling packet, the PKT_TX_UDP_TUNNEL_PKT flag must be set to enable tunneling packet TX checksum offload for both outer layer and inner layer.
Refer to the testpmd source code (specifically the csumonly.c file) for details.

That being said, the support of some offload features implies the addition of dedicated status bit(s) and value field(s) into the rte_mbuf data structure, along with their appropriate handling by the receive/transmit functions exported by each PMD.

For instance, this is the case for the IEEE1588 packet timestamp mechanism, the VLAN tagging and the IP checksum computation, as described in the Section 7.6 “Meta Information”.

8.4.4. Configuration of Transmit and Receive Queues

Each transmit queue is independently configured with the following information:

• The number of descriptors of the transmit ring
• The socket identifier used to identify the appropriate DMA memory zone from which to allocate the transmit ring in NUMA architectures
• The values of the Prefetch, Host and Write-Back threshold registers of the transmit queue
• The minimum transmit packets to free threshold (tx_free_thresh).

When the number of descriptors used to transmit packets exceeds this threshold, the network adaptor should be checked to see if it has written back descriptors.
A value of 0 can be passed during the TX queue configuration to indicate the default value should be used.
The default value for tx_free_thresh is 32.
This ensures that the PMD does not search for completed descriptors until at least 32 have been processed by the NIC for this queue.

• The minimum RS bit threshold. The minimum number of transmit descriptors to use before setting the Report Status (RS) bit in the transmit descriptor. Note that this parameter may only be valid for Intel 10 GbE network adapters. The RS bit is set on the last descriptor used to transmit a packet if the number of descriptors used since the last RS bit setting, up to the first descriptor used to transmit the packet, exceeds the transmit RS bit threshold (tx_rs_thresh). In short, this parameter controls which transmit descriptors are written back to host memory by the network adapter. A value of 0 can be passed during the TX queue configuration to indicate that the default value should be used. The default value for tx_rs_thresh is 32. This ensures that at least 32 descriptors are used before the network adapter writes back the most recently used descriptor. This saves upstream PCIe* bandwidth resulting from TX descriptor write-backs. It is important to note that the TX Write-back threshold (TX wthresh) should be set to 0 when tx_rs_thresh is greater than 1. Refer to the Intel® 82599 10 Gigabit Ethernet Controller Datasheet for more details.

• 送信リングのデスクリプタの数
• NUMAアーキテクチャで送信リングを割り当てるのに適切なDMAメモリ領域を識別するために使用されるソケット識別子
• プリフェッチ、ホスト、送信キューのライトバックしきい値レジスタの値
• 送信パケットを開放するための最小のしきい値（tx_free_thresh）。\ パケットを送信するために使用されるデスクリプタの数が、このしきい値を超えたときに、ネットワークアダプタは、ディスクリプタをライトバックしているかどうかがチェックされるべきである。

• 最小 RSビットの閾値。送信ディスクリプタにレポートステータス（RS）ビットを設定する前に、使用する送信ディスクリプタの最小数。 このパラメータは、インテルの10 GbEネットワークアダプターに対して有効であることに注意してください。 最後のRSビットの設定から使用さ記述子の数は、パケットを送信するために使用される第1の記述子まで、送信RSビット閾値（tx_rs_thresh）を超える。RSビットは、パケットを送信するために使用される最後の記述子に設定されている 要するに、記述子を伝送するこのパラメータを制御し、ネットワークアダプタによってホストメモリに書き戻される。 0の値は、デフォルト値が使用されるべきであることを示すために、TXキューを構成中に通過させることができる。 tx_rs_threshのデフォルト値は、このネットワークアダプタは、最も最近使用された記述子を書き戻す前に、少なくとも32の記述子が使用されることを保証する32である。 これは、TXディスクリプタライトバックから生じる上流のPCIe *帯域幅を節約できます。 それはtx_rs_threshは詳細についてはインテル®82599 10ギガビットイーサネットコントローラデータシートを参照してください1よりも大きい場合、TXライトバックしきい値（TXのwthresh）が0に設定されるべきことに注意することが重要です。

The following constraints must be satisfied for tx_free_thresh and tx_rs_thresh:
- tx_rs_thresh must be greater than 0.
- tx_rs_thresh must be less than the size of the ring minus 2.
- tx_rs_thresh must be less than or equal to tx_free_thresh.
- tx_free_thresh must be greater than 0.
- tx_free_thresh must be less than the size of the ring minus 3.
- For optimal performance, TX wthresh should be set to 0 when tx_rs_thresh is greater than 1.
One descriptor in the TX ring is used as a sentinel to avoid a hardware race condition, hence the maximum threshold constraints.

• tx_rs_threshは 0より大きくなければなりません。
• tx_rs_threshは リングのサイズ-2 よりも 小さくなければなりません。
• tx_rs_threshは tx_free_thresh以下でなければなりません。
• tx_free_threshは 0より大きくなければなりません。
• tx_free_threshは リングのサイズ -3 よりも 小さくなければなりません。
• tx_rs_threshが 1より大きい場合に最適なパフォーマンスを得るには、TX wthreshは0に設定する必要があります。

Note When configuring for DCB operation, at port initialization, both the number of transmit queues and the number of receive queues must be set to 128.

8.5. Poll Mode Driver API¶

8.5.1. Generalities¶

By default, all functions exported by a PMD are lock-free functions that are assumed not to be invoked in parallel on different logical cores to work on the same target object.
For instance, a PMD receive function cannot be invoked in parallel on two logical cores to poll the same RX queue of the same port.
Of course, this function can be invoked in parallel by different logical cores on different RX queues.
It is the responsibility of the upper-level application to enforce this rule.

If needed, parallel accesses by multiple logical cores to shared queues can be explicitly protected by dedicated inline lock-aware functions built on top of their corresponding lock-free functions of the PMD API.

8.5.2. Generic Packet Representation （一般論）

A packet is represented by an rte_mbuf structure, which is a generic metadata structure containing all necessary housekeeping information.
This includes fields and status bits corresponding to offload hardware features, such as checksum computation of IP headers or VLAN tags.

The rte_mbuf data structure includes specific fields to represent, in a generic way, the offload features provided by network controllers.
For an input packet, most fields of the rte_mbuf structure are filled in by the PMD receive function with the information contained in the receive descriptor.
Conversely, for output packets, most fields of rte_mbuf structures are used by the PMD transmit function to initialize transmit descriptors.

The mbuf structure is fully described in the Mbuf Library chapter.

8.5.3. Ethernet Device API

The Ethernet device API exported by the Ethernet PMDs is described in the DPDK API Reference.

8.6. Vector PMD for IXGBE

Vector PMD uses Intel® SIMD instructions to optimize packet I/O.
It improves load/store bandwidth efficiency of L1 data cache by using a wider SSE/AVX register 1 (1).
The wider register gives space to hold multiple packet buffers so as to save instruction number when processing bulk of packets.

There is no change to PMD API.
The RX/TX handler are the only two entries for vPMD packet I/O.
They are transparently registered at runtime RX/TX execution if all condition checks pass.

1. To date, only an SSE version of IX GBE vPMD is available.
To ensure that vPMD is in the binary code, ensure that the option CONFIG_RTE_IXGBE_INC_VECTOR=y is in the configure file.

Some constraints apply as pre-conditions for specific optimizations on bulk packet transfers.
The following sections explain RX and TX constraints in the vPMD.

8.6.1. RX Constraints

8.6.1.1. Prerequisites and Pre-conditions

The following prerequisites apply:
- To enable vPMD to work for RX, bulk allocation for Rx must be allowed.
- The RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC=y configuration MACRO must be set before compiling the code.

• RXのためにvPMDを有効にするには、Rxのためのバルク割り当てが許可されなければならない。
• RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC = Yの構成マクロは、コードをコンパイルする前に設定する必要があります。

Ensure that the following pre-conditions are satisfied:
- rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
- rxq->rx_free_thresh < rxq->nb_rx_desc
- (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
- rxq->nb_rx_desc < (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)
These conditions are checked in the code.

Scattered packets are not supported in this mode.
If an incoming packet is greater than the maximum acceptable length of one “mbuf” data size (by default, the size is 2 KB), vPMD for RX would be disabled.

By default, IXGBE_MAX_RING_DESC is set to 4096 and RTE_PMD_IXGBE_RX_MAX_BURST is set to 32.

• rxq-> rx_free_thresh> = RTE_PMD_IXGBE_RX_MAX_BURST
• rxq-> rx_free_thresh nb_rx_desc
• （rxq-> nb_rx_desc％rxq-> rx_free_thresh）== 0
• rxq-> nb_rx_desc <（IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST）

8.6.1.2. Feature not Supported by RX Vector PMD

Some features are not supported when trying to increase the throughput in vPMD.
They are:
- IEEE1588
- FDIR
- Header split
- RX checksum off load

Other features are supported using optional MACRO configuration. They include:
- HW VLAN strip
- HW extend dual VLAN
- Enabled by RX_OLFLAGS (RTE_IXGBE_RX_OLFLAGS_DISABLE=n)

To guarantee the constraint, configuration flags in dev_conf.rxmode will be checked:
- hw_vlan_strip
- hw_vlan_extend
- hw_ip_checksum
- header_split
- dev_conf
fdir_conf->mode will also be checked.

8.6.1.3. RX Burst Size

As vPMD is focused on high throughput, it assumes that the RX burst size is equal to or greater than 32 per burst.
It returns zero if using nb_pkt < 32 as the expected packet number in the receive handler.

8.6.2. TX Constraint （送信制約）

8.6.2.1. Prerequisite （前提条件）

The only prerequisite is related to tx_rs_thresh.
The tx_rs_thresh value must be greater than or equal to RTE_PMD_IXGBE_TX_MAX_BURST, but less or equal to RTE_IXGBE_TX_MAX_FREE_BUF_SZ.
Consequently, by default the tx_rs_thresh value is in the range 32 to 64.

8.6.2.2. Feature not Supported by RX Vector PMD

TX vPMD only works when txq_flags is set to IXGBE_SIMPLE_FLAGS.
This means that it does not support TX multi-segment, VLAN offload and TX csum offload.
The following MACROs are used for these three features:
- ETH_TXQ_FLAGS_NOMULTSEGS
- ETH_TXQ_FLAGS_NOVLANOFFL
- ETH_TXQ_FLAGS_NOXSUMSCTP
- ETH_TXQ_FLAGS_NOXSUMUDP
- ETH_TXQ_FLAGS_NOXSUMTCP

• ETH_TXQ_FLAGS_NOMULTSEGS
• ETH_TXQ_FLAGS_NOVLANOFFL
• ETH_TXQ_FLAGS_NOXSUMSCTP
• ETH_TXQ_FLAGS_NOXSUMUDP
• ETH_TXQ_FLAGS_NOXSUMTCP

8.6.3. Sample Application Notes

22. IP Fragmentation and Reassembly Library

The IP Fragmentation and Reassembly Library implements IPv4 and IPv6 packet fragmentation and reassembly.

22.1. Packet fragmentation

Packet fragmentation routines devide input packet into number of fragments.
Both rte_ipv4_fragment_packet() and rte_ipv6_fragment_packet() functions assume that input mbuf data points to the start of the IP header of the packet
(i.e. L2 header is already stripped out).
To avoid copying for the actual packet's data zero-copy technique is used (rte_pktmbuf_attach).
For each fragment two new mbufs are created:

• Direct mbuf – mbuf that will contain L3 header of the new fragment.
• Indirect mbuf – mbuf that is attached to the mbuf with the original packet. It's data field points to the start of the original packets data plus fragment offset.

• ダイレクトmbuf: 新しいフラグメントのL3ヘッダを構成するmbuf
• インダイレクトmbuf: オリジナルパケットにattachされたmbuf. このデータフィールドはオリジナルパケットデータの先頭にフラグメントオフセットを加算した位置を指している。

Then L3 header is copied from the original mbuf into the 'direct' mbuf and updated to reflect new fragmented status.
Note that for IPv4, header checksum is not recalculated and is set to zero.

Finally 'direct' and 'indirect' mbufs for each fragnemt are linked together via mbuf's next filed to compose a packet for the new fragment.

The caller has an ability to explicitly specify which mempools should be used to allocate 'direct' and 'indirect' mbufs from.

Note that configuration macro RTE_MBUF_SCATTER_GATHER has to be enabled to make fragmentation library build and work correctly.
For more information about direct and indirect mbufs, refer to the DPDK Programmers guide "7.7 Direct and Indirect Buffers".

22.2. Packet reassembly

22.2.1. IP Fragment Table

Fragment table maintains information about already received fragments of the packet.

Each IP packet is uniquely identified by triple , , .

Note that all update/lookup operations on Fragmen Table are not thread safe.
So if different execution contexts (threads/processes) will access the same table simultaneously, then some exernal syncing mechanism have to be provided.

Each table entry can hold information about packets consisting of up to RTE_LIBRTE_IP_FRAG_MAX (by default: 4) fragments.

Code example, that demonstrates creation of a new Fragment table:

Internally Fragment table is a simple hash table.
The basic idea is to use two hash functions and * associativity.
This provides 2 * possible locations in the hash table for each key.
When the collision occurs and all 2 * are occupied, instead of reinserting existing keys into alternative locations, ip_frag_tbl_add() just returns a faiure.