dqsのポート設定を誤ってoutportとして接続したとき，Synthesisまで通ってしまった． その後のTimingQuestによるtiming analysisで，TimeQuestがassertionでこけた．（QuartusII v8.1, WEB edition） 本件，属性違いに気づかずALTERA my supportにてSRを出してしまったが，Work Aroundとして"inout"にしてくださいといわれて気づいた．
デフォルトでは，このコマンドはPLLを駆動する入力クロックポートに基準クロック（base clock）を作りません．By default this command does not create base clocks on input clock ports that are driving the PLL.
"create_base_clocks"オプションを使うとき，"derive_pll_clocks"もまたPLLを駆動する入力クロックポート上の基準クロックを作ります．When you use the create_base_clocks option, derive_pll_clocks also creates the base clock on an input clock port deriving the PLL.このオプションは既存のクロックを上書きしません．デフォルトでは，クロック名は出力クロック端子名と同じになります．ネット名を使う（同じ名前は，クラシックなTiming Analyzerが使います）ためには，"-use_tan_name"オプションを使用してください．
project_open top
create_timing_netlist
# Create the base clock for the input clock port driving the PLL
create_clock -period 10.0 [get_ports sysclk]
# Create the generated clocks for the PLL.
derive_pll_clocks
update_timing_netlist
# Other user actions
report_timing
delete_timing_netlist
project_close
# Get regout pin of "reg" cell
get_pins -nocase reg|regout
# Create a collection of all pins of "reg" cell
get_pins reg|*
# Create a collection of all pins on the highest hierarachical level
set mycollection [get_pins *]
# Output pin names.
foreach_in_collection pin $mycollection {
puts [get_pin_info -name $pin]
}
# Create a collection of all pins in the design
set fullcollection [get_pins -hierarchical *]
# Output pin IDs and names.
foreach_in_collection pin $fullcollection {
puts -nonewline $pin
puts -nonewline ": "
puts [get_pin_info -name $pin]
}
project_open top
create_timing_netlist
create_clock -period 10.000 -name clkA [get_ports sysclk[0]]
create_clock -period 10.000 -name clkB [get_ports sysclk[1]]
# Set clkA and clkB to be mutually exclusive clocks.
set_clock_groups -exclusive -group {clkA} -group {clkB}
# The previous line is equivalent to the following two commands.
set_false_path -from [get_clocks clkA] -to [get_clocks clkB]
set_false_path -from [get_clocks clkB] -to [get_clocks clkA]
Active Serial/Active Parallelをenableにした場合，そのピンが使用されているような警告画でます．コレを回避するためには，QuartusIIのデバイス設定をいじくると良いようです． 図の例はActive Parallelの例です．config後の端子をどうするかを選択できます．ユーザ定義のIOとして使う場合は，図のように"Use as regular I/O"とすればOKです．
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "flash_reset_n" is stuck at VCC
Warning (13410): Pin "sram_flash_a[0]" is stuck at GND
[HELP]
CAUSE: The output pins are minimized to either VCC or GND in a design file. This condition may be the result of the optimization process performed during logic synthesis.
ACTION: If you intend the output pins to behave in this manner, no action is required. Otherwise, check the design file for errors and ensure that the project's logic does not reduce to VCC or GND.
Warning: Feature LogicLock is not available with your current license
これまたライセンスがない．
Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
[HELP]
CAUSE: There are one or more pins with incomplete I/O assignments. The I/O Assignment Warnings report section in the Fitter compilation report lists the affected pins and the missing I/O assignments.
ACTION: Use the Assignment Editor or the Pin Planner to add the missing I/O assignments to the affected pins.
たぶん，以下のピンアサインをさしていると思う．
Warning: No exact pin location assignment(s) for 1 pins of 82 total pins
Info: Pin sram_flash_a[0] not assigned to an exact location on the device
virtual指定していたピン．未配線なので捨ててよいとおもう．
Warning: At least one of the filters had some problems and could not be matched.
Warning: *the*clock*|unxmaster*donex*|*data* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_registers *] -to [get_pins -nocase -compatibility_mode {*the*clock*|unxmaster*donex*|*data*}]
Warning: Argument -to with value [get_pins -nocase -compatibility_mode {*the*clock*|unxmaster*donex*|*data*}] contains zero elements
Warning: At least one of the filters had some problems and could not be matched.
Warning: *the*clock*|unxslave*requestx*|*data* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_registers *] -to [get_pins -nocase -compatibility_mode {*the*clock*|unxslave*requestx*|*data*}]
Warning: Argument -to with value [get_pins -nocase -compatibility_mode {*the*clock*|unxslave*requestx*|*data*}] contains zero elements
Warning: At least one of the filters had some problems and could not be matched.
Warning: *the*clock*|slave_address*|* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_address*|*}] -to [get_registers *]
Warning: Argument -from with value [get_pins -nocase -compatibility_mode {*the*clock*|slave_address*|*}] contains zero elements
Warning: At least one of the filters had some problems and could not be matched.
Warning: *the*clock*|slave_byteenable*|* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_byteenable*|*}] -to [get_registers *]
Warning: Argument -from with value [get_pins -nocase -compatibility_mode {*the*clock*|slave_byteenable*|*}] contains zero elements
Warning: The master clock for this clock assignment could not be derived. Clock: altera_internal_jtag|tckutap was not created.
Warning: No clocks found on or feeding the specified source node: altera_internal_jtag|tck
Warning: Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment.
Warning: The following clock transfers have no clock uncertainty assignment
Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Fall) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[2] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Fall) (setup and hold)
Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[1] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[2] (Rise) (setup and hold)
Warning: From osc_clk (Rise) to osc_clk (Rise) (setup and hold)
Warning: Ignored I/O standard assignments to the following nodes
Warning: Ignored locations or region assignments to the following nodes
Warning:
The total number of single-ended output or bi-directional pins in Bank 8 exceeded the recommended amount in a bank where dedicated LVDS, RSDS or mini-LVDS outputs exists.
Such condition may result in excessive output jitter on the differential outputs at condition where all the single-ended outputs are switching simultaneously.
Refer to the Pad Placement and DC Guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition.
Info: There are 28 output pin(s) with I/O standard 2.5 V and current strength 8mA.
Info: Location E10 (pad PAD_213) : Pin sram_flash_a[16] of type output uses 2.5 V I/O standard
Info: Location C9 (pad PAD_214) : Pin sram_flash_a[17] of type output uses 2.5 V I/O standard
Info: Location D9 (pad PAD_215) : Pin sram_flash_a[18] of type output uses 2.5 V I/O standard
Info: Location A8 (pad PAD_218) : Pin sram_flash_d[2] of type bi-directional uses 2.5 V I/O standard
Info: Location B8 (pad PAD_219) : Pin sram_flash_d[3] of type bi-directional uses 2.5 V I/O standard
Info: Location A7 (pad PAD_220) : Pin sram_flash_a[19] of type output uses 2.5 V I/O standard
Info: Location B7 (pad PAD_221) : Pin sram_flash_d[4] of type bi-directional uses 2.5 V I/O standard
Info: Location A6 (pad PAD_222) : Pin sram_flash_a[20] of type output uses 2.5 V I/O standard
Info: Location B6 (pad PAD_223) : Pin sram_flash_d[15] of type bi-directional uses 2.5 V I/O standard
Info: Location C7 (pad PAD_224) : Pin sram_flash_d[31] of type bi-directional uses 2.5 V I/O standard
Info: Location A5 (pad PAD_225) : Pin sram_flash_d[14] of type bi-directional uses 2.5 V I/O standard
Info: Location B5 (pad PAD_226) : Pin sram_flash_d[13] of type bi-directional uses 2.5 V I/O standard
Info: Location C5 (pad PAD_227) : Pin sram_flash_d[5] of type bi-directional uses 2.5 V I/O standard
Info: Location D7 (pad PAD_228) : Pin sram_flash_d[27] of type bi-directional uses 2.5 V I/O standard
Info: Location F9 (pad PAD_230) : Pin sram_ce_n of type output uses 2.5 V I/O standard
Info: Location E8 (pad PAD_231) : Pin sram_flash_d[6] of type bi-directional uses 2.5 V I/O standard
Info: Location A4 (pad PAD_232) : Pin sram_flash_d[7] of type bi-directional uses 2.5 V I/O standard
Info: Location B4 (pad PAD_233) : Pin sram_flash_d[8] of type bi-directional uses 2.5 V I/O standard
Info: Location E7 (pad PAD_234) : Pin sram_flash_d[9] of type bi-directional uses 2.5 V I/O standard
Info: Location F8 (pad PAD_235) : Pin sram_flash_d[26] of type bi-directional uses 2.5 V I/O standard
Info: Location A3 (pad PAD_236) : Pin sram_flash_d[10] of type bi-directional uses 2.5 V I/O standard
Info: Location B3 (pad PAD_237) : Pin sram_flash_d[11] of type bi-directional uses 2.5 V I/O standard
Info: Location E6 (pad PAD_238) : Pin sram_flash_d[29] of type bi-directional uses 2.5 V I/O standard
Info: Location F7 (pad PAD_239) : Pin sram_adsc_n of type output uses 2.5 V I/O standard
Info: Location F6 (pad PAD_241) : Pin sram_flash_d[28] of type bi-directional uses 2.5 V I/O standard
Info: Location D5 (pad PAD_242) : Pin sram_flash_d[12] of type bi-directional uses 2.5 V I/O standard
Info: Location A2 (pad PAD_246) : Pin sram_clk of type output uses 2.5 V I/O standard
Info: Location G6 (pad PAD_247) : Pin sram_flash_d[30] of type bi-directional uses 2.5 V I/O standard
Info: There are 1 output pin(s) with I/O standard 2.5 V and current strength 12mA.
Info: Location E9 (pad PAD_216) : Pin sram_oe_n of type output uses 2.5 V I/O standard
Warning: Following 2 pins must use external clamping diodes.
Info: Pin sram_flash_d[0] uses I/O standard 2.5 V at H3
Info: Pin sram_flash_d[1] uses I/O standard 2.5 V at D1
外部のクランプダイオードを用意するように言われるが，schematic見ても無いような気が...?
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin flash_reset_n has VCC driving its datain port
Info: Pin sram_flash_a[0] has GND driving its datain port
[HELP]
CAUSE: The specified pins either have nothing, GND, or VCC driving the datain port.
If you modify this setting, additional pin placement restrictions such as simultaneously switching outputs may be necessary and may lead to a change in the fitting results.
ACTION: If you do not intend to connect these pins, no action is required. Otherwise, modify the design to reflect the required connectivity.
Warning: At least one of the filters had some problems and could not be matched.
Warning: *|the_pll_0|the_pll|altpll_component|auto_generated|pll1|clk[1] could not be matched with a clock.
[HELP]
CAUSE: At least one of the filters cannot be matched with an element.
ACTION: Change the filter to match with at least one element.
