fpga(跡地)

FPGAをまともにいじるのは初めてのソフト屋，を前提ですすめます．ここではsynthesisするときに出てきたwarningとその対策を記します．ただし，個人的解釈に基づくメモであり，記述漏れ，誤記，解釈誤りがありえます．
間違いを指摘いただけますと幸いです..

で，SOPC Builderで新規に作った構成を記しておきます．評価キットのsampleを持ってきたわけではないので，大量にWarningが出てきます．サンプルですら出てきますが．．．

前もって設定する事項

Active Serial/Active Parallelをenableにした場合，そのピンが使用されているような警告画でます．コレを回避するためには，QuartusIIのデバイス設定をいじくると良いようです．
図の例はActive Parallelの例です．config後の端子をどうするかを選択できます．ユーザ定義のIOとして使う場合は，図のように"Use as regular I/O"とすればOKです．

Processing windowのWarningについて（Quartus II Analysis & Synthesis）

Warning: Output pins are stuck at VCC or GND
  Warning (13410): Pin "flash_reset_n" is stuck at VCC
  Warning (13410): Pin "sram_flash_a[0]" is stuck at GND

[HELP]
 CAUSE: The output pins are minimized to either VCC or GND in a design file. This condition may be the result of the optimization process performed during logic synthesis.
 ACTION: If you intend the output pins to behave in this manner, no action is required. Otherwise, check the design file for errors and ensure that the project's logic does not reduce to VCC or GND.

記述ミスや設定ミスにより意図しない出力値固定となることもあるので，レベルが固定されたピンを確認しておく．

Warning: Feature Virtual IO is not available with your current license

Virtual I/O宣言を処理するためのライセンスがない．グループ開発で有用なものだったはず．無償評価版では使えない．合成結果で，ピン配置が異様でなければOKとする．

Processing windowのWarningについて（Quartus II Fitter）

Warning: Feature LogicLock is not available with your current license

これまたライセンスがない．

Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

[HELP]
 CAUSE: There are one or more pins with incomplete I/O assignments. The I/O Assignment Warnings report section in the Fitter compilation report lists the affected pins and the missing I/O assignments.
 ACTION: Use the Assignment Editor or the Pin Planner to add the missing I/O assignments to the affected pins.

たぶん，以下のピンアサインをさしていると思う．

Warning: No exact pin location assignment(s) for 1 pins of 82 total pins
  Info: Pin sram_flash_a[0] not assigned to an exact location on the device

virtual指定していたピン．未配線なので捨ててよいとおもう．

Warning: At least one of the filters had some problems and could not be matched.
	Warning: *the*clock*|unxmaster*donex*|*data* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_registers *] -to [get_pins -nocase -compatibility_mode {*the*clock*|unxmaster*donex*|*data*}]
	Warning: Argument -to with value [get_pins -nocase -compatibility_mode {*the*clock*|unxmaster*donex*|*data*}] contains zero elements
Warning: At least one of the filters had some problems and could not be matched.
	Warning: *the*clock*|unxslave*requestx*|*data* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_registers *] -to [get_pins -nocase -compatibility_mode {*the*clock*|unxslave*requestx*|*data*}]
	Warning: Argument -to with value [get_pins -nocase -compatibility_mode {*the*clock*|unxslave*requestx*|*data*}] contains zero elements
Warning: At least one of the filters had some problems and could not be matched.
	Warning: *the*clock*|slave_address*|* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_address*|*}] -to [get_registers *]
	Warning: Argument -from with value [get_pins -nocase -compatibility_mode {*the*clock*|slave_address*|*}] contains zero elements
Warning: At least one of the filters had some problems and could not be matched.
	Warning: *the*clock*|slave_byteenable*|* could not be matched with a pin.
Warning: Ignored assignment: set_false_path -from [get_pins -nocase -compatibility_mode {*the*clock*|slave_byteenable*|*}] -to [get_registers *]
	Warning: Argument -from with value [get_pins -nocase -compatibility_mode {*the*clock*|slave_byteenable*|*}] contains zero elements

Warning: The master clock for this clock assignment could not be derived.  Clock: altera_internal_jtag|tckutap was not created.
	Warning: No clocks found on or feeding the specified source node: altera_internal_jtag|tck
Warning: Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment.

Warning: The following clock transfers have no clock uncertainty assignment
	Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
	Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Fall) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
	Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[2] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
	Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Fall) (setup and hold)
	Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[1] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
	Warning: From Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0] (Rise) to Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[2] (Rise) (setup and hold)
	Warning: From osc_clk (Rise) to osc_clk (Rise) (setup and hold)

Warning: Ignored I/O standard assignments to the following nodes
Warning: Ignored locations or region assignments to the following nodes

実際に端子名が列挙されますが，省略します．DDR-SDRAMのlocaltion設定を記述していたので，そんなものないから制約から消しますよ，というメッセージになります．
記述誤りで無視されることもありえるので，ココもチェック必要です*1．

Warning:
 The total number of single-ended output or bi-directional pins in Bank 8 exceeded the recommended amount in a bank where dedicated LVDS, RSDS or mini-LVDS outputs exists.
 Such condition may result in excessive output jitter on the differential outputs at condition where all the single-ended outputs are switching simultaneously.
 Refer to the Pad Placement and DC Guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition.
	Info: There are 28 output pin(s) with I/O standard 2.5 V and current strength 8mA.
		Info: Location E10 (pad PAD_213) : Pin sram_flash_a[16] of type output uses 2.5 V I/O standard
		Info: Location C9 (pad PAD_214) : Pin sram_flash_a[17] of type output uses 2.5 V I/O standard
		Info: Location D9 (pad PAD_215) : Pin sram_flash_a[18] of type output uses 2.5 V I/O standard
		Info: Location A8 (pad PAD_218) : Pin sram_flash_d[2] of type bi-directional uses 2.5 V I/O standard
		Info: Location B8 (pad PAD_219) : Pin sram_flash_d[3] of type bi-directional uses 2.5 V I/O standard
		Info: Location A7 (pad PAD_220) : Pin sram_flash_a[19] of type output uses 2.5 V I/O standard
		Info: Location B7 (pad PAD_221) : Pin sram_flash_d[4] of type bi-directional uses 2.5 V I/O standard
		Info: Location A6 (pad PAD_222) : Pin sram_flash_a[20] of type output uses 2.5 V I/O standard
		Info: Location B6 (pad PAD_223) : Pin sram_flash_d[15] of type bi-directional uses 2.5 V I/O standard
		Info: Location C7 (pad PAD_224) : Pin sram_flash_d[31] of type bi-directional uses 2.5 V I/O standard
		Info: Location A5 (pad PAD_225) : Pin sram_flash_d[14] of type bi-directional uses 2.5 V I/O standard
		Info: Location B5 (pad PAD_226) : Pin sram_flash_d[13] of type bi-directional uses 2.5 V I/O standard
		Info: Location C5 (pad PAD_227) : Pin sram_flash_d[5] of type bi-directional uses 2.5 V I/O standard
		Info: Location D7 (pad PAD_228) : Pin sram_flash_d[27] of type bi-directional uses 2.5 V I/O standard
		Info: Location F9 (pad PAD_230) : Pin sram_ce_n of type output uses 2.5 V I/O standard
		Info: Location E8 (pad PAD_231) : Pin sram_flash_d[6] of type bi-directional uses 2.5 V I/O standard
		Info: Location A4 (pad PAD_232) : Pin sram_flash_d[7] of type bi-directional uses 2.5 V I/O standard
		Info: Location B4 (pad PAD_233) : Pin sram_flash_d[8] of type bi-directional uses 2.5 V I/O standard
		Info: Location E7 (pad PAD_234) : Pin sram_flash_d[9] of type bi-directional uses 2.5 V I/O standard
		Info: Location F8 (pad PAD_235) : Pin sram_flash_d[26] of type bi-directional uses 2.5 V I/O standard
		Info: Location A3 (pad PAD_236) : Pin sram_flash_d[10] of type bi-directional uses 2.5 V I/O standard
		Info: Location B3 (pad PAD_237) : Pin sram_flash_d[11] of type bi-directional uses 2.5 V I/O standard
		Info: Location E6 (pad PAD_238) : Pin sram_flash_d[29] of type bi-directional uses 2.5 V I/O standard
		Info: Location F7 (pad PAD_239) : Pin sram_adsc_n of type output uses 2.5 V I/O standard
		Info: Location F6 (pad PAD_241) : Pin sram_flash_d[28] of type bi-directional uses 2.5 V I/O standard
		Info: Location D5 (pad PAD_242) : Pin sram_flash_d[12] of type bi-directional uses 2.5 V I/O standard
		Info: Location A2 (pad PAD_246) : Pin sram_clk of type output uses 2.5 V I/O standard
		Info: Location G6 (pad PAD_247) : Pin sram_flash_d[30] of type bi-directional uses 2.5 V I/O standard
	Info: There are 1 output pin(s) with I/O standard 2.5 V and current strength 12mA.
		Info: Location E9 (pad PAD_216) : Pin sram_oe_n of type output uses 2.5 V I/O standard

SingleEndの端子が多すぎてジッタが乗ったりしても知らないよ，とのこと．まぁ大丈夫だろ...
DDRを使うときは，同じバンクにあるLEDの端子を未使用にすること．IO制約により使えなくなる．

Warning: Following 2 pins must use external clamping diodes.
	Info: Pin sram_flash_d[0] uses I/O standard 2.5 V at H3
	Info: Pin sram_flash_d[1] uses I/O standard 2.5 V at D1

外部のクランプダイオードを用意するように言われるが，schematic見ても無いような気が...?

Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
	Info: Pin flash_reset_n has VCC driving its datain port
	Info: Pin sram_flash_a[0] has GND driving its datain port

[HELP]
 CAUSE: The specified pins either have nothing, GND, or VCC driving the datain port.
        If you modify this setting, additional pin placement restrictions such as simultaneously switching outputs may be necessary and may lead to a change in the fitting results.
 ACTION: If you do not intend to connect these pins, no action is required. Otherwise, modify the design to reflect the required connectivity.

端子出力が固定になっていますというメッセージのようですね．
問題がなければ無視してもいいでしょう．

Warningについて（Quartus II Assembler）

Warning: Can't convert time-limited SOF into POF, HEX File, TTF, or RBF

NiosII評価ライセンスだとこうなる．買えばOK...

TimeQuest Timing Analyzerの吐くmessageについて

Warning: At least one of the filters had some problems and could not be matched.
 Warning: *|the_pll_0|the_pll|altpll_component|auto_generated|pll1|clk[1] could not be matched with a clock.

[HELP]
 CAUSE: At least one of the filters cannot be matched with an element.
 ACTION: Change the filter to match with at least one element.

false_path設定のところで，パターンマッチングに失敗した旨の表示．これは自分で作った制約ファイルでの話しなので，修正は必要．PLL出力をパターンマッチングで抽出し，clock domain境界でタイミングチェックを行わないようにするため．
bridgeを介在しているため，チェックする必要がないpathのみのdomainをノーチェックとしている．

ガバッと省略(書き溜め不足)

Critical Warning: Timing requirements not met

Info: Path #1: Hold slack is -2.284 (VIOLATED)
  Info: ===================================================================
  Info: From Node    : sram_flash_d[5]
  Info: To Node      : Nios2_NoDDR:Nios2_NoDDR_inst|pipeline_bridge_m1_arbitrator:the_pipeline_bridge_m1|dbs_latent_16_reg_segment_0[5]
  Info: Launch Clock : Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[2]
  Info: Latch Clock  : Nios2_NoDDR_inst|the_pll0|the_pll|altpll_component|auto_generated|pll1|clk[0]
  Info: Multicycle - Setup End   : 2
  Info:
  Info: Data Arrival Path:
  Info:
  Info: Total (ns)  Incr (ns)     Type  Element
  Info: ==========  ========= ==  ====  ===================================
  Info:      0.000      0.000           launch edge time
  Info:      1.058      1.058  R        clock network delay
  Info:      5.158      4.100  R  iExt  sram_flash_d[5]
  Info:      5.158      0.000 RR    IC  sram_flash_d[5]~input|i
  Info:      5.520      0.362 RR  CELL  sram_flash_d[5]~input|o
  Info:      7.631      2.111 RR    IC  Nios2_NoDDR_inst|the_pipeline_bridge_m1|dbs_latent_16_reg_segment_0[5]~feeder|datab
  Info:      7.785      0.154 RR  CELL  Nios2_NoDDR_inst|the_pipeline_bridge_m1|dbs_latent_16_reg_segment_0[5]~feeder|combout
  Info:      7.785      0.000 RR    IC  Nios2_NoDDR_inst|the_pipeline_bridge_m1|dbs_latent_16_reg_segment_0[5]|d
  Info:      7.816      0.031 RR  CELL  Nios2_NoDDR:Nios2_NoDDR_inst|pipeline_bridge_m1_arbitrator:the_pipeline_bridge_m1|dbs_latent_16_reg_segment_0[5]
  Info:
  Info: Data Required Path:
  Info:
  Info: Total (ns)  Incr (ns)     Type  Element
  Info: ==========  ========= ==  ====  ===================================
  Info:     10.000     10.000           latch edge time
  Info:     10.169      0.169  R        clock network delay
  Info:     10.253      0.084      uTh  Nios2_NoDDR:Nios2_NoDDR_inst|pipeline_bridge_m1_arbitrator:the_pipeline_bridge_m1|dbs_latent_16_reg_segment_0[5]
  Info:
  Info: Data Arrival Time  :     7.816
  Info: Data Required Time :    10.253
  Info: Clock Pessimism    :     0.153
  Info: Slack              :    -2.284 (VIOLATED)
  Info: ===================================================================
  Info:

論理合成後にタイミング違反を検出．これはSSRAMへ供給しているクロックと，データ信号との制約に対する違反（Violation）ですね．
図を描けば確認できるかと思いますが，Hold timeのslackを救おうとしても，Setupとの兼ね合いもあるので，単純には解決できない模様です．

ここで注目すべきはSSRAM CLKです．
starterkitのサンプルを見ていて，systemで使っているクロックと同じ100MHzなのにPLL出力が違ったのです．未確認ですが位相をずらして制約をカバーしているのではないかと踏んだわけです．
少し端折りますが，位相をずらして対策をいれたときの，TimeQuest Timing Analyzerを使って図示させます．

SSRAM CLKを2.5nSec早めることでHold Timeを稼ぐことができました．synthesisをやり直しているので，全く同じ回路でPLL遅延だけが変化したのかはわかりかねますが，Timing Errorを回避させました．
とはいえ，今回はLaunch ClockとLatch Clockとが異なっていたのでできた回避作ですね．

図中，Pane-3に波形が図示されますが，Pane-1にはドコでどの程度時間を消費しているかの詳細がわかります．最適化の変更や回路設計そのものの変更などにより，その時間を調整する必要があるのでしょうが，その時限の話はまたぶちあたった時にでも考えましょう．